- 08 Apr, 2020 4 commits
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Alex Deucher authored
fixes unused variable warning. Reported-by:
Eric Biggers <ebiggers@kernel.org> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Mikita Lipski <mikita.lipski@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Aaron Liu authored
Make the fw_write_wait default case true since presumably all new gfx9 asics will have updated firmware. That is using unique WAIT_REG_MEM packet with opration=1. Signed-off-by:
Aaron Liu <aaron.liu@amd.com> Tested-by:
Yuxian Dai <Yuxian.Dai@amd.com> Acked-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Evan Quan authored
For Arcturus, forcing clock to some specific level is not supported with 54.18 and onwards SMU firmware. As according to firmware team, they adopt new gfx dpm tuned parameters which can cover all the use case in a much smooth way. Thus setting through driver interface is not needed and maybe do a disservice. Signed-off-by:
Evan Quan <evan.quan@amd.com> Reviewed-by:
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Prike Liang authored
The system will be hang up during S3 suspend because of SMU is pending for GC not respose the register CP_HQD_ACTIVE access request.This issue root cause of accessing the GC register under enter GFX CGGPG and can be fixed by disable GFX CGPG before perform suspend. v2: Use disable the GFX CGPG instead of RLC safe mode guard. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Tested-by:
Mengbing Wang <Mengbing.Wang@amd.com> Reviewed-by:
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- 07 Apr, 2020 14 commits
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Michael Strauss authored
[WHY] In cases where a clock table is malformed such that fclk entries have frequencies but not voltages listed, we don't catch the error and set clocks to 0 instead of using hardcoded values as we should. [HOW] Add check for clock tables fclk entry's voltage as well Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
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Joshua Aberback authored
[Why] If dc->clk_mgr->funcs->are_clock_states_equal is set, then wm_optimized_required is never checked. In that case, when going from a higher mode to a lower mode, wm_optimized_required remains true until the next mode change. [How] - move from else-if to unconditional or Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] In some usecases, like tiled display, the stream and plane configuration can be setup in a way where the caller expects DAL to perform the clipping, eg: P0: src_rect(0, 0, w, h) dst_rect(0, 0, w, h) P1: src_rect(w, 0, w, h) dst_rect(0, 0, w, h) Cursor is enabled on both streams with the same position. This can result in double cursor on tiled display, even though this behavior is technically correct from the DC interface point of view. We need a mechanism to control this dynamically. [How] This is something that should live in the DM layer based on detection of the specified configuration but it's not something that we really have enough information to deal with today. Add a flag to the cursor position state that specifies whether we want DC to do the translation or not and make it opt-in and let the DM decide when to do it. Signed-off-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] If a plane isn't being actively enabled or disabled then DC won't always recalculate scaling rects and ratios for the primary plane. This results in only a partial or corrupted rect being displayed on the screen instead of scaling to fit the screen. [How] Add back the logic to recalculate the scaling rects into dc_commit_updates_for_stream since this is the expected place to do it in DC. This was previously removed a few years ago to fix an underscan issue but underscan is still functional now with this change - and it should be, since this is only updating to the latest plane state getting passed in. Signed-off-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] For medium updates that change nothing but the source rect position the viewport doesn't change on DCN20. We're missing the check for the position update bit that was there in the DCN10 hardware sequencer. [How] Check the position bit along with the scaling bit like we were doing with DCN20. We shouldn't actually hit a case where context != current_state in our programming/commit model but guard against it anyway since it was guarded for the other bits. Signed-off-by:
Zhan Liu <Zhan.Liu@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] Cursor pos is correctly adjusted from DC side for source rect offset on DCN ASIC, but only on the overlay. This is because DM places offsets the cursor for primary planes only to workaround missing code in DCE for the adjustment we're now correctly doing in DC for DCN ASIC. [How] Drop the adjustment for source rect from the DM side of things and put the code where it actually belongs - in DC on the pipe level. This matches what we do for DCN now. Signed-off-by:
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Eric Yang authored
[Why] Changing policy to dynamic will allow 4k multi display configs to be supported at DPM0 Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Cursor is drawn as part of the framebuffer for a plane on AMD hardware. The cursor position on the framebuffer does not change even if the source rect viewport for the cursor does. This causes the cursor to be clipped. The following IGT tests fail as a result of this issue: - kms_plane_cursor@pipe-*-viewport-size-* [How] Offset cursor position by plane source rect viewport. If the viewport is unscaled then the cursor is now correctly positioned on any plane - primary or overlay. There is still a hardware limitation for dealing with the cursor size being incorrectly scaled but that's not something we can address. Add some documentation explaining some of this in the code while we're at it. Signed-off-by:
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Isabel Zhang authored
[Why] After v_total_min and max are updated in vrr structure, the changes are not reflected in stream adjust. When these values are read from stream adjust it does not reflect the actual state of the system. [How] Set stream adjust values equal to vrr adjust values after vrr adjust values are updated. Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
Alvin Lee <Alvin.Lee2@amd.com> Acked-by:
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Jerry (Fangzhi) Zuo authored
[Why] Prop are created at boot stage, and not allowed to create new prop after device registration. [How] Reuse the connector property from SST if exist. Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Alex Deucher authored
Replace dev_warn() with dev_info() and note that they are optional to avoid confusing users. The RAS TAs only exist on server boards and the HDCP and DTM TAs only exist on client boards. They are optional either way. Acked-by:
Nirmoy Das <nirmoy.das@amd.com> Signed-off-by:
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John Clements authored
prefix RAS error related dmesg print with pci device info Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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John Clements authored
upon receiving uncorrectable error, query every GPU node for ras errors Reviewed-by:
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Chengming Gui authored
Incorrect CG sequence will cause gfx timedout, if we keep switching power profile mode (enter profile mod such as PEAK will disable CG, exit profile mode EXIT will enable CG) when run Vulkan test case(case used for test: vkexample). Signed-off-by:
Chengming Gui <Jack.Gui@amd.com> Reviewed-by:
Kenneth Feng <kenneth.feng@amd.com> Acked-by:
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- 03 Apr, 2020 6 commits
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Aaron Ma authored
On ARCTURUS and RENOIR, powerplay is not supported yet. When plug in or unplug power jack, ACPI event will issue. Then kernel NULL pointer BUG will be triggered. Check for NULL pointers before calling. Signed-off-by:
Aaron Ma <aaron.ma@canonical.com> Signed-off-by:
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Likun Gao authored
Change SH_MEM_CONFIG Alignment mode to Automatic, as: 1)OGL fn_amd_compute_shader will failed with unaligned mode. 2)The default alignment mode was defined to automatic on gfx10 specification. Signed-off-by:
Likun Gao <Likun.Gao@amd.com> Reviewed-by:
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Tiecheng Zhou authored
hwmgr->pm_en is initialized at hwmgr_hw_init. during amdgpu_device_init, there is amdgpu_asic_reset that calls to pp_get_asic_baco_capability, while hwmgr->pm_en has not yet been initialized. so avoid using pm_en in pp_get_asic_baco_capability. Reviewed-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
Yintian Tao <yttao@amd.com> Signed-off-by:
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Prike Liang authored
As the pmfw hasn't exported the interface of SMU feature mask to APU SKU so just force on all the features to driver inquired interface at early initial stage. Signed-off-by:
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Shirish S authored
Fixes build error of: "use of undeclared identifier 'RENOIR_A0'" To fix the same, this patch re-orders the ASIC declarations accordingly. Fixes: 41ef3dcd ("drm/amd/display: Fix RV2 Variant Detection") Signed-off-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Yuxian Dai authored
1.Using the FCLK DPM table to set the MCLK for DPM states consist of three entities: FCLK UCLK MEMCLK All these three clk change together, MEMCLK from FCLK, so use the fclk frequency. 2.we should show the current working clock freqency from clock table metric Signed-off-by:
Kevin Wang <Kevin1.Wang@amd.com> Signed-off-by:
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- 01 Apr, 2020 1 commit
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Jack Zhang authored
Originally, it kfrees the wrong pointer for mem_obj. It would cause memory leak under stress test. Signed-off-by:
Jack Zhang <Jack.Zhang1@amd.com> Acked-by:
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- 31 Mar, 2020 15 commits
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Bhawanpreet Lakha authored
[Why] Some displays have an issue where the hdcp chips are initialized after the display has already lit up. This means we can sometimes authentication too early and cause authentication failures. This happens when HDCP is enabled and the display is power cycled. Normally we will authenticate 2 seconds after the display is lit, but some displays need a bit more time. [How] Increase delay to 3 second before we start authentication. Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
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Bhawanpreet Lakha authored
[Why] -We need to cancel future callbacks/watchdogs events when a callback/watchdog event happens [How] -fix typo in event_callback() -cancel callback, not watchdog -cancel watchdog events in event_watchdog_timer(). Signed-off-by:
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Bhawanpreet Lakha authored
[Why] When content type property is set to 1. We should enable hdcp2.2 and if we cant then stop. Currently the way it works in DC is that if we fail hdcp2, we will try hdcp1 after. [How] Use link config to force disable hdcp1.4 when type1 is set. Signed-off-by:
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Evan Quan authored
This is ASIC specific and should be placed in _ppt.c of each ASIC. Signed-off-by:
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Evan Quan authored
This is already done in soc15.c. And this is really ASIC specific and should not be placed here. Signed-off-by:
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Dmytro Laktyushkin authored
[Why] DML expects num_states to exclude the duplicate state. [How] Set num_states to correct value to prevent array off-by-one error. Also refactor max clock level code for diags. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Signed-off-by:
George Shen <george.shen@amd.com> Reviewed-by:
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Stylon Wang authored
[Why] BT2020 is not supported in COLOR_ENCODING property of planes. Only BT601 and BT709 was available. [How] Allow BT2020 as legit value in setting COLOR_ENCODING property. Signed-off-by:
Stylon Wang <stylon.wang@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] Nominal pixel clock and EDID information differ in precision so although monitor reports maximum refresh is 2x minimum, LFC was not being enabled. [How] Use minimum refresh rate as nominal/2 when EDID dictates that min refresh = max refresh/2. v2: squash in 64 bit divide fix Signed-off-by:
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Stylon Wang authored
[Why] CTM was only supported at CRTC level and we need color space conversion in linear space at plane level. [How] - Add plane-level CTM to dc interface - Program plane-level CTM in DCN Signed-off-by:
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Isabel Zhang authored
[Why] Change is causing a regression where the OPC app no longer functions properly. [How] Revert the changelist causing the issue. Signed-off-by:
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Yongqiang Sun authored
[Why] In some scenario like 1366x768 VSR enabled connected with a 4K monitor and playing 4K video in clone mode, underflow will be observed due to decrease dppclk when previouse surface scan isn't finished [How] In this use case, surface flip is switching between 4K and 1366x768, 1366x768 needs smaller dppclk, and when decrease the clk and previous surface scan is for 4K and scan isn't done, underflow will happen. Not doing optimize bandwidth in case of flip pending. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] For some monitors extreme flickering can occur while using LFC for if we're not doing the DRR timing update for V_TOTAL_MIN / V_TOTAL_MAX at the DP start of frame. Hardware can default to any time in the frame which isn't the behavior we want. [How] Add a new function for setting the double buffering mode for DRR timing. Default to DP start of frame double buffering on timing generator init. Signed-off-by:
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Stylon Wang authored
[Why] P010 pixel format is not declared as supported in DRM and DM. [How] Add P010 format to the support list presented to DRM and checked in DM Signed-off-by:
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Eric Bernstein authored
[Why] Diagnostics scaling test failing to set required number of vertical taps in 4:2:0 surface case [How] In dpp3_get_optimal_number_of_taps() need to use LB_MEMORY_CONFIG_3 for 4:2:0 surface case. In resource_build_scaling_params() make sure to also set plane res alpha enable based on updated surface state Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Kevin Wang authored
the HPD bo size calculation error. the "mem.size" can't present actual BO size all time. Signed-off-by:
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