- 08 Nov, 2013 40 commits
-
-
Ben Widawsky authored
BDW-A workaround BDW Bug #1899155 Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch>
-
Ben Widawsky authored
BDW-A workaround. BDW Bug #1899812 Signed-off-by:
-
Ben Widawsky authored
BDW-A workaround BDW Bug #1899532 v2: WARN on when not using preliminary HW support Signed-off-by:
Jesse Barnes <jbarnes@virtuosugeek.org> Signed-off-by:
-
Ben Widawsky authored
Signed-off-by:
-
Ben Widawsky authored
This implements a workaround for PSR dealing with some vblank issue. WaPsrDPAMaskVBlankInSRD && WaPsrDPRSUnmaskVBlankInSRD v2: forgot to git add bogus whitespace fix v3: Update with workaround names. Use for_each_pipe() and CHICKEN_PIPESL_1(pipe) macro (Ville) Cc: Art Runyan <arthur.j.runyan@intel.com> Signed-off-by:
-
Ben Widawsky authored
We've done insufficient testing on them thus far, so keep them disabled until we do test. v2: Use WARN when not enabling preliminary HW support as this should only be disabled for that case. v3: Rip out the now useless (and really noisy) DRM_INFO output. Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
-
Ben Widawsky authored
This is mostly what we have for HSW with the exceptions of: no writes: GEN6_RC1_WAKE_RATE_LIMIT GEN6_RC6pp_WAKE_RATE_LIMIT GEN6_RC1e_THRESHOLD GEN6_RC6p_THRESHOLD GEN6_RC6pp_THRESHOLD GEN6_RP_DOWN_TIMEOUT - use 1s instead of 1.28s Don't try to overclock, or program ring/IA frequency tables since we don't quite have sufficient docs yet. NOTE: These values do not reflect the changes made recently by Chris. Since we have no evidence yet what the proper way to tweak for this platform is, I think it is good to go, and can be optimized by Chris, or whomever, later. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
-
Damien Lespiau authored
Just like HSW. This means we can scan out a mode with a 300Mhz pixel clock with a depth of 24 bits, but only a 200Mhz one with a 36bits depth. Signed-off-by:
Damien Lespiau <damien.lespiau@intel.com> Reviewed-by:
Jani Nikula <jani.nikula@intel.com> Signed-off-by:
-
Ben Widawsky authored
It's no longer a required workaround on BDW. Signed-off-by:
-
Ben Widawsky authored
The current formula we use for HSW is not what is in current docs. However, changing to the HSW formula on my HSW does not improve power usage, and decreases performance by about 5% in limited xonotic testing. For gen8, until we know otherwise, or run experiments, let's use the HSW formula - which should be the same used in the Windows driver (and thus help make an apples-applies comparison) on gen8. v2: Use >= 8 instead of > 7 to be consistent with all other gen checks. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by: -
Ben Widawsky authored
Broadwell PSR support is a superset of Haswell. With this simple register base calculation, everything that worked on HSW for eDP PSR should work on BDW. Note that Broadwell provides additional PSR support. This is not addressed at this time. v2: Make the HAS_PSR include BDW v3: Use the correct offset (I had incorrectly used one from my faulty brain) (Art!) v4: It helps if you git add v5: Be explicit about not setting min link entry time for BDW. This should be no functional change over v4 (Jani) Reviewed-by:
Art Runyan <arthur.j.runyan@intel.com> Reviewed-by:
-
Ben Widawsky authored
v2: Squash in fixup from Ben to synchronize the GT mailbox commands. CC: Art Runyan <arthur.j.runyan@intel.com> Reviewed-by:
-
Ville Syrjälä authored
Broadwell has bigger display FIFOs than Haswell. Otherwise the two are very similar. v2: Fix FBC WM_LP shift for BDW v3: Rebase on top of the big Haswell wm rework. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> (v2) Reviewed-by:
-
Paulo Zanoni authored
Use the eDP values on platforms where port D is eDP. This doesn't affect Haswell since it uses the same DDI buffer values for eDP and DP. Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by:
-
Paulo Zanoni authored
So treat it like Haswell. Reviewed-by:
-
Paulo Zanoni authored
They're not the same as the Haswell ones. Reviewed-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
-
Paulo Zanoni authored
Broadwell has different DDI buffer translations for eDP and DP, so add support for the missing eDP and keep Haswell the same. A future patch addresses the suggestion from Art to check for eDP on port D and use the eDP values there, too. v2: Make checkpatch happy. Reviewed-by:
-
Art Runyan authored
Many of the DDI buffer translation values have changed for BDW. Add new translation tables and selection between HSW and BDW. v2: s/BUG/WARN/ to avoid breaking future GENs. v3: Rebase on top of the hdmi translation table changes. v4: Fix up the multiline comment while at it. Signed-off-by: Art Runyan <arthur.j.runyan@intel.com> (v2) Reviewed-by:
-
Ben Widawsky authored
GEN8 also needs this workaround. Signed-off-by:
-
Ville Syrjälä authored
Route cursor and sprite data through the pipe CSC unit on BDW. Primary plane data is already sent through the pipe CSC. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
-
Paulo Zanoni authored
v2: Rebased onto Paulo's MHz->kHz change. v3: Rebased on top of the Haswell pc8+ adjustements. v4: Use the exact 337.5MHz clock, should have been done as part of v2. Reviewed-by:
-
Paulo Zanoni authored
And it inherits some bits from the previous TRANS_CONF (aka PIPE_CONF on previous gens). v2: Rebase on to of the pipe config bpp handling rework. v3: Rebased on top of the pipe_config->dither refactoring. v4: Drop the read-modify-write cycle for PIPEMISC, similarly to how we now also build up PIPECONF completely ourselves - keeping around random stuff set by the BIOS just isn't a good idea. I've checked BDW BSpec and we already set all relevant bits. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
-
Paulo Zanoni authored
So you can use the panel fitter while the power well is disabled and you also don't need to set the "pipe" bit. v2: Rebased on top of Jesse's pfit refactor, which moved pfit state into the pipe_config. v3: Rebase on top of the latest Haswell/panel fitter rework, which neatly resolves a FIXME we have in this patch here: v4: Rebase on top of the new power domain framework. Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
-
Paulo Zanoni authored
The platforms we currently have all have LPT LP on them. As such, we have no way to identify the new WPT PCH that will ship with Broadwell. NOTE: For all purposes relevant to the driver that this point, LPT and WPT are equivalent. Therefore there should be no need to actually change this for some time. v2: Don't assign dev_priv->num_pch_pll any more. v3: Rebase on top of the PCH detection changes for virtualized enviroments. v4: Wrote commit message Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> (v3) Signed-off-by:
-
Paulo Zanoni authored
Just like Haswell, but with the small twist that the panel fitter for pipe A is now also in the always-on power well. v2: Use the new HAS_POWER_WELL macro. v3: Rebase on top of intel_using_power_well patches. v4: This time actually update the PFIT check correctly so that the pipe A pfit is in the always-on domain. v5: Rebase on top of the VGA power domain addition. v6: Rebase on top of the new power domain infrastructure. Also pimp the commit message a bit while at it. v7: Use IS_BROADWELL instead of IS_GEN8 (Ville). Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v1) Reviewed-by:
-
Paulo Zanoni authored
Just make Broadwell follow the same code paths as Haswell here, instead of running code for the even-older platforms. v2: Shuffle around Ben's vma prep work. Reviewed-by:
-
Damien Lespiau authored
v2: Rebase (Paulo Zanoni) v3: Rebase on top of num_pipes having moved to intel_device_info. Signed-off-by: Damien Lespiau <damien.lespiau@intel.com> (v1) Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> (v2) Signed-off-by: -
Paulo Zanoni authored
For now it's just equivalent to IS_GEN8, but in the future we might want to change that (e.g., on Gen 7 we have IS_VALLEYVIEW, IS_IVYBRIDGE and IS_HASWELL). Signed-off-by:
-
Ben Widawsky authored
This was an oversight and should have been in a previous series somewhere. Signed-off-by:
-
Ben Widawsky authored
It's not so much that the information is terribly useful, but rather that the gen6/7 information is completely useless. Signed-off-by:
-
Ville Syrjälä authored
v2: Resolve rebase conflicts and switch to gen < 8 color for GenX checking. v3: Rebase on top of the address space refactoring. Reviewed-by:
-
Ben Widawsky authored
PIPE_CONTROL added the high address dword. I'm not sure how the simulator let me get away with this. I've explicitly left out all the workarounds from Gen7 because in the minimal digging that I did, most don't seem necessary, and the simulator doesn't complain without them Note that BLT and BSD ring commands had already been updated previously. Just render/pipe_control should have been broken. v2: Squash in a fixup from Ville to follow the recent IVB PIPE_CONTROL updates: "BDW uses the IVB PIPE_CONTROL style for specifying GTT vs. PPGTT for the PIPE_CONTROL QW/DW write." v3: Rebase on top of Chris' cleanup to have an explicit ring->scratch buffer object instead of an opaque ring->private where everyone stores the same stuff inside. Reported-by:
-
Ben Widawsky authored
v2: Squash in fix from Ben: Set PPGTT batches as necessary This fixes the regression in the last couple of days when we enabled PPGTT. v3: Squash in fixup to still use GTT for secure batches from Ville: BDW doesn't have a separate secure vs. non-secure bit in MI_BATCH_BUFFER_START. So for secure batches we have to simply leave the PPGTT bit unset. Fortunately older generations (except HSW) had similar limitations so execbuffer already creates a GTT mapping for all secure batches. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Imre Deak <imre.deak@intel.com> Signed-off-by:
-
Ben Widawsky authored
Legacy PPGTT on GEN8 requires programming 4 PDP registers per ring. Since all rings are using the same address space with the current code the logic is simply to program all the tables we've setup for the PPGTT. v2: Turn on PPGTT in GFX_MODE v3: v2 was the wrong patch v4: Resolve conflicts due to patch series reordering. v5: Squash in fixup from Ben: Use LRI to write PDPs The docs (and simulator seems to back up) suggest that we can only program legacy PPGTT PDPs with LRI commands. v6: Rebase around context differences conflicts. v7: Use #defines for per ring PDPs. (Damien) v8: Don't use typede'f private_t. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (up to v3 and v7) Reviewed-by:
-
Ben Widawsky authored
GEN8 insertion is very similar to GEN6. v2: Rebase on top of Imre's for_each_sg_page helpers. v3: Fixup my conversion (spotted by Ville). v4: Rebase on top of the address space refactoring. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Reviewed-by:
-
Ben Widawsky authored
GEN8 PPGTT range clearing is very similar to GEN6 if we assume that our PDEs are all valid, which they should be. v2: Rebase on top of the address space refactoring. v3: Rebase on top of the bool use_scratch addition to the clear_range interface. Reviewed-by:
-
Ben Widawsky authored
The upcoming clear and insert routines will expect that PDEs all point to valid Page Directories. Doing that lazily doesn't really buy us anything. The page allocation is done regardless earlier in init so it shouldn't hurt set the PDEs. v2: Squash in patches to implement fixed PDE write function: - If I had done this in the first place, the bug that's going to be fixed in an upcoming patch would have been much easier to find. - Use WB for PDEs. The PAT bit is used for page size. 2ME PDEs aren't even supported in BDW, so this was completely invalid. The solution is to make our PDEs WB+LLC instead of the pervious WB+eLLC. As far as I can guess, this change won't matter for performance. Thanks to Ville for the quick correction when discussing on IRC. v3: Return the pde type for pde encoding (Damien) Reviewed-by:
-
Ben Widawsky authored
Aside from the potential size increase of the PPGTT, the primary difference from previous hardware is the Page Directories are no longer carved out of the Global GTT. Note that the PDE allocation is done as a 8MB contiguous allocation, this needs to be eventually fixed (since driver reloading will be a pain otherwise). Also, this will be a no-go for real PPGTT support. v2: Move vtable initialization v3: Resolve conflicts due to patch series reordering. v4: Rebase on top of the address space refactoring of the PPGTT support. Drop Imre's r-b tag for v2, too outdated by now. v5: Free the correct amount of memory, "get_order takes size not a page count." (Imre) Signed-off-by:
-
Ben Widawsky authored
BDW caching works differently than the previous generations. Instead of having bits in the PTE which directly control how the page is cached, the 3 PTE bits PWT PCD and PAT provide an index into a PAT defined by register 0x40e0. This style of caching is functionally equivalent to how it works on HSW and before. v2: Tiny bikeshed as discussed on internal irc. v3: Squash in patch from Ville to mirror the x86 PAT setup more like in arch/x86/mm/pat.c. Primarily, the 0th index will be WB, and not uncached. v4: Comment for reason to not use a 64b write on the PPAT. v5: Add a FIXME comment that the caching bits in the PAT registers might be wrong due to doc confusion. Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Signed-off-by:
-
Ben Widawsky authored
With the PTE clarifications, the bind and clear functions can now be added for gen8. v2: Use for_each_sg_pages in gen8_ggtt_insert_entries. v3: Drop dev argument to pte encode functions, upstream lost it. Also rebase on top of the scratch page movement. v4: Rebase on top of the new address space vfuncs. v5: Add the bool use_scratch argument to clear_range and the bool valid argument to the PTE encode function to follow upstream changes. v6: Add a FIXME(BDW) about the size mismatch of the readback check that Jon Bloomfield spotted. v7: Squash in fixup patch from Ben for the posting read to match the 64bit ptes and so shut up the WARN. Signed-off-by: Ben Widawsky <ben@bwidawsk.net> (v1) Reviewed-by:
-
