- 07 Apr, 2017 3 commits
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Christopher James Halse Rogers authored
Migration to VRAM will break the sharing, resulting in rendering on the exporting GPU never becoming visible on the importing GPU. v2: Don't pin BOs to GTT. Instead, refuse to migrate them out of GTT. Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Christopher James Halse Rogers <christopher.halse.rogers@canonical.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christopher James Halse Rogers authored
Any use of the framebuffer will migrate it to VRAM, which is not sensible for an imported dma-buf. v2: Use DRM_DEBUG_KMS to prevent userspace accidentally spamming dmesg. Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Christopher James Halse Rogers authored
Any use of the framebuffer will migrate it to VRAM, which is not sensible for an imported dma-buf. v2: Use DRM_DEBUG_KMS to prevent userspace accidentally spamming dmesg. Reviewed-by:
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- 06 Apr, 2017 37 commits
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git://people.freedesktop.org/~agd5f/linuxDave Airlie authored
A few more things for 4.12: - ttm and amdgpu support for non-contiguous vram CPU mappings - lots of bug fixes and cleanups for vega10 - misc bug fixes and code cleanups [airlied: fix do_div error on 32-bit arm, not sure it's 100% correct] * 'drm-next-4.12' of git://people.freedesktop.org/~agd5f/linux: (58 commits) drm/amdgpu: use uintptr_t instead of unsigned long to store pointer drm/amdgpu: Avoid using signed integer to store pointer value drm/amdgpu:invoke new implemented AI MB func drm/amdgpu/vega10:timeout set to equal with VI drm/amdgpu:implement the reset MB func for vega10 drm/amdgpu:fix typo for mxgpu_ai drm/amdgpu:no need to involv HDP in KIQ drm/amdgpu:add PSP block only load_type=PSP (v2) drm/amdgpu/smu9: update to latest driver interface drm/amd/amdgpu: cleanup gfx_v9_0_gpu_init() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_reset() drm/amd/amdgpu: cleanup gfx_v9_0_rlc_start() drm/amd/amdgpu: simplify gfx_v9_0_cp_gfx_enable() drm/amd/amdgpu: cleanup gfx_v9_0_kiq_init_register() drm/amd/amdgpu: Drop gfx_v9_0_print_status() drm/amd/amdgpu: cleanup gfx_v9_0_set_gfx_eop_interrupt_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_reg_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_set_priv_inst_fault_state() drm/amd/amdgpu: cleanup gfx_v9_0_init_queue() drm/amdgpu: Move function amdgpu_has_atpx near other similar functions ...
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https://git.pengutronix.de/git/lst/linuxDave Airlie authored
Highlights: - Cooling device support from Russell, to allow GPU throttling on system thermal overload. - Explicit fencing support from Philipp, implemented in a similar way to drm/msm. * 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux: drm/etnaviv: submit support for out-fences drm/etnaviv: return GPU fence through the submit structure drm/etnaviv: submit support for in-fences drm/etnaviv: add etnaviv cooling device drm/etnaviv: switch to postclose drm/etnaviv: add lockdep assert to fence allocation
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git://git.pengutronix.de/git/pza/linuxDave Airlie authored
imx-drm module/dependency changes - The PRE/PRG drivers added an unwanted DRM dependency to the ipu-v3 driver. Remove the dependency by conditionally disabling PRE/PRG support depending on CONFIG_DRM. - Merge the imx-ipuv3-crtc module into the imxdrm module. There is no reason anymore for a separation between core drm driver and crtc/plane drivers, especially since commit eb8c8880 ("drm/imx: add deferred plane disabling"), which added a dependency on imx-ipuv3-crtc to the imxdrm module. * tag 'imx-drm-next-2017-04-04' of git://git.pengutronix.de/git/pza/linux: drm/imx: merge imx-drm-core and ipuv3-crtc in one module gpu: ipu-v3: don't depend on DRM being enabled
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git://github.com/skeggsb/linuxDave Airlie authored
A bit more for 4.12: - GP10B support - GP107 acceleration support * 'linux-4.12' of git://github.com/skeggsb/linux: (23 commits) drm/nouveau/gpio: enable interrupts on cards with 32 gpio lines drm/nouveau/gr/gp107: initial support drm/nouveau/core: recognise GP10B chipset drm/nouveau/platform: support for probing GP10B drm/nouveau/platform: make VDD regulator optional drm/nouveau/gr: support for GP10B drm/nouveau/ibus: add GP10B support drm/nouveau/mc: add GP10B support drm/nouveau/fb: add GP10B support drm/nouveau/fifo: add GP10B support drm/nouveau/msgqueue: support for GP10B PMU firmware drm/nouveau/secboot: add GP10B support drm/nouveau/secboot/gm20b: specify MC base address as argument drm/nouveau/secboot: start LS firmware in post-run hook drm/nouveau/secboot: let LS post_run hooks return error drm/nouveau/secboot: pass instance to LS firmware loaders drm/nouveau/secboot: allow to boot multiple falcons drm/nouveau/imem/gk20a: Turn instmem lock into mutex drm/nouveau: initial support (display-only) for GP107 drm/nouveau/kms/nv50: fix double dma_fence_put() when destroying plane state ...
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Alex Xie authored
Signed-off-by:
Alex Xie <AlexBin.Xie@amd.com> Reviewed-by:
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Alex Xie authored
Signed-off-by:
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Monk Liu authored
Implement the sr-iov mailbox for soc15 asics. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
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Monk Liu authored
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Monk Liu authored
they are lack in the bringup stage, we need them for GPU reset feature. Signed-off-by:
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Monk Liu authored
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Monk Liu authored
1,KIQ won't touch VRAM so no need to involv HDP flush/invalidate at all. 2,According to CP hw designer KIQ better not use any PM4 package lead to wait behave. Signed-off-by:
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Monk Liu authored
SRIOV currently only can load ucode directly, and PSP block is not supported by VF temporarily. will remove this restrict and use PSP load all ucode even for SRIOV later v2: squash in check against module parameter Signed-off-by:
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Evan Quan authored
Signed-off-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD macro Signed-off-by:
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Tom St Denis authored
It's not used in gfx 6/7/8 so drop it from gfx 9 as well. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD15 macro. Signed-off-by:
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Tom St Denis authored
Introduce WREG32_FIELD15 macro for SOC15 architectures. Signed-off-by:
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Alex Xie authored
Signed-off-by:
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Christian König authored
We need an array of pointers to IRQ sources, not an array of sources. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Had the wrong sense in the loop Signed-off-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: keep the function pointer Signed-off-by:
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Zhang, Jerry authored
Set reasonable defaults per family. v2: set both of them in gmc v3: move vm size and block size in vm manager v4: squash in warning fix from Alex Xie v5: squash in min() warning fix Signed-off-by:
Junwei Zhang <Jerry.Zhang@amd.com> Reviewed-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Clean up a toggle with ?:. Signed-off-by:
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Tom St Denis authored
Signed-off-by:
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Swap read/write pattern for WREG32_FIELD() Signed-off-by:
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Tom St Denis authored
Use new WREG32_FIELD_OFFSET() to clean up code. Signed-off-by:
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Alex Deucher authored
Set the ready flag to reflect this. Reviewed-by:
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Christian König authored
The two hubs are just instances of the same hardware, so the register bits are identical. v2: only remove get_vm_protection_bits for now Signed-off-by:
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