An error occurred fetching the project authors.
- 12 Apr, 2017 3 commits
-
-
Xiaofei Tan authored
This patch adds a workaround solution for a SoC bug which may cause SoC logic fatal error when disabling a PHY. Then we find internal abort IO timeout may occur, and the controller IO breakpoint may be corrupted. We work around this SoC bug by optimizing the flow of disabling a PHY. Signed-off-by:
Xiaofei Tan <tanxiaofei@huawei.com> Signed-off-by:
John Garry <john.garry@huawei.com> Signed-off-by:
Martin K. Petersen <martin.petersen@oracle.com>
-
Xiaofei Tan authored
This patch provides a workaround a SoC bug where SATA IPTTs for different devices may conflict. The workaround solution requests the following: 1. SATA device id must be even and not equal to SAS IPTT. 2. SATA device can not share the same IPTT with other SAS or SATA device. Besides we shall consider IPTT value 0 is reserved for another SoC bug (STP device open link at firstly after SAS controller reset). To sum up, the solution is: Each SATA device uses independent and continuous 32 even IPTT from 64 to 4094, then v2 hw can only support 63 SATA devices. All SAS device(SSP/SMP devices) share odd IPTT value from 1 to 4095. Signed-off-by:
Johannes Thumshirn <jthumshirn@suse.de> Signed-off-by:
-
Xiaofei Tan authored
After resetting the controller, the process of scanning SATA disks attached to an expander may fail occasionally. The issue is that the controller can't close the STP link created by target if the max link time is 0. To workaround this issue, we reject STP link after resetting the controller, and change the corresponding PHY to accept STP link only after receiving data. We do this check in cq interrupt handler. In order not to reduce efficiency, we use an variable to control whether we should check and change PHY to accept STP link. The function phys_reject_stp_links_v2_hw() should be called after resetting the controller. The solution of another SoC bug "SATA IO timeout", that also uses the same register to control STP link, is not effective before the PHY accepts STP link. Signed-off-by:
-
- 30 Mar, 2017 1 commit
-
-
Colin Ian King authored
It appears that a break in the TRANS_TX_OPEN_CNX_ERR_NO_DESTINATION case got accidentally removed in an earlier commit, as it stands, the ts->stat and ts->open_rej_reason are being updated twice for this case which looks incorrect. Fix this by adding in the missing break statement. Detected by CoverityScan, CID#1422110 ("Missing break in switch") Fixes: 634a9585 ("scsi: hisi_sas: process error codes according to their priority") Signed-off-by:Colin Ian King <colin.king@canonical.com> Acked-by:
-
- 23 Mar, 2017 14 commits
-
-
Xiaofei Tan authored
Add helper function is_sata_phy_v2_hw() to judge whether the attached device is SATA disk for a root PHY. Signed-off-by:
-
John Garry authored
For consistency, remove the "hisi_sas_" prefix. Signed-off-by:
-
Xiaofei Tan authored
Handle the situation that PHY UP and DOWN irq happen simultaneously. There is no mechanism of SoC HW to ensure this situation will never happen. So, we add this handle just in case. Signed-off-by:
-
John Garry authored
This patch includes: (1) Disable transport layer retry (2) Support CQ time and count interrupt coal (3) fix link FIFO full issue Signed-off-by:
Xiang Chen <chenxiang66@hisilicon.com> Signed-off-by:
Zhao Nenglong <zhaonenglong@hisilicon.com> Signed-off-by:
-
Xiang Chen authored
There are some rules to decide which error code has the high priority when errors happen together: (1) Error phase of CQ decides the error happens on RX or TX; (2) For TX error, when DMA/TRANS TX error happen simultaneously, the priority of DMA TX error is higher than TRANS TX error, so for the priority of TX error: DW2 (DMA TX part) > DW0; (3) For RX error, when TRANS/DMA/SIPC RX error happen simultaneously, the priority of TRANS RX error is higher than DMA and SIPC RX error, and we should also keep the rules (the priority of DW3 > DW2), so for the priority of RX error: DW1 > DW3 > DW2(SIPC RX part); (4) There are also a priority we should keep in the same error type. So, modify slot error code to handle this. In addition to this, some some error codes are modified according to recommendation from SoC designer. Signed-off-by: -
John Garry authored
Some more locking needs to be added/modified for when read-modify-writing sas_task.task_state_flags. Note: since we can attempt to grab this lock in interrupt context we should use irq variant of spin_lock. Signed-off-by: -
John Garry authored
Check in slot_complete_v2_hw() for whether a task has already been completed by upper layer. Signed-off-by:
-
John Garry authored
Currently an internal abort is executed regardless of the result of the TMF. We should also check the result of the internal abort to see if we should free the slot. So change the status code STAT_IO_COMPLETE to TMF_RESP_FUNC_SUCC, meaning the slot has been successfully aborted. Signed-off-by:
-
Xiang Chen authored
For error codes which need abort-and-retry, simulate IO timeout and let SCSI+ATA layers process those errors. Previously for SSP, we should try to abort the IO in the LLDD and then pass back to upper layer, but sometimes this would also error. So Instead of adding special error handling for this scenario in the LLDD, allow the upper layer to handle completely. No performance hit is seen by taking this approach. Signed-off-by:
-
John Garry authored
Currently when a root PHY is deformed from a asd_sas_port we try to release the slots in the LLDD, and fail. Regardless, it is not right to release this early. This patch removes the deformed function. As it was before, port deformation is still done in hisi_sas_phy_down(). It would be nice to actually remove the hisi_sas_port_{de}formed() pair, however we cannot as we need to know the asd_sas_port index libsas has associated with an asd_sas_phy. The hw does actually generate a port id for a PHY, but this seems to a random number, so ignored for this purpose. This patch also changes the code to link slots to the hisi_sas_device, and not hisi_sas_port. Signed-off-by: -
Xiang Chen authored
Add softreset to clear IO after internal abort device for SATA disk. The SATA error handling for the controller is based on device internal abort and softreset function. The controller does not support internal abort for single IO, so we need to execute internal abort for device. Signed-off-by:
-
John Garry authored
Relocate the PHY init code from LLDD hw init path to hisi_sas_scan_start(). Signed-off-by:
-
Xiang Chen authored
There are some scenarios that we need to warm-reset to reset registers of SAS controller. During reset we disable interrupts/DQs/PHYs, and after reset we re-init the hardware and rescan the topology to see if anything changed. Signed-off-by:
-
John Garry authored
Introduce function to get hisi_sas_port from asd_sas_port. Signed-off-by:
-
- 21 Jan, 2017 5 commits
-
-
Xiang Chen authored
There is an issue that hisi_sas_dev.running_req is not decremented properly for internal abort and TMF. To resolve, only decrease running_req in hisi_sas_slot_task_free() Signed-off-by:
-
Xiang Chen authored
There is a potential probe issue in how we trigger the hw initialisation. Although we use 1s timer to delay hw initialisation, there is still a potential that sas_register_ha() is not be finished before we start the PHY init from hw->hw_init(). To avoid this issue, initialise the hw after sas_register_ha() in the same probe context. Note: it is not necessary to use 1s timer now (modified v2 hw only). Signed-off-by:
-
Xiang Chen authored
Correctly set registers in v2 for root PHY hardreset for directly attached disk. Signed-off-by:
-
Xiang Chen authored
Set SMP connection timeout and continue AWT timer; Clear ITCT table when dev gone. Signed-off-by:
-
Xiang Chen authored
The v2 SAS controller needs more time to detect channel idle and send setup link request than SATA disk does, so it is difficult for the SAS controller to setup an STP link. Therefore it may cause some IO timeouts. We need to periodically configure the SAS controller so it doesn't receive STP setup requests from SATA disks for a while, so IO can be sent during this period. Signed-off-by:
-
- 05 Jan, 2017 2 commits
-
-
John Garry authored
There is a bug in the current driver in that certain hisi_hba and port structure elements which we access when servicing the CQ interrupt do not use thread-safe accesses; these include hisi_sas_port linked-list of active slots (hisi_sas_port.entry), bitmap of currently allocated IPTT (in hisi_hba.slot_index_tags), and completion queue read pointer. As a solution, lock these elements with the hisi_hba.lock. Signed-off-by:
Zhangfei Gao <zhangfei.gao@linaro.org> Tested-by:
Hanjun Guo <hanjun.guo@linaro.org> Signed-off-by:
-
John Garry authored
Currently the all the slot processing for the completion queue is done in ISR context. It is judged that the slot processing can take a long time, especially when a SATA NCQ completes (upto 32 slots). So, as a solution, defer the bulk of the ISR processing to tasklet context. Each CQ will have its down tasklet. Signed-off-by:
-
- 07 Dec, 2016 1 commit
-
-
John Garry authored
In the hip06 and hip07 SoCs, the interrupt lines from the SAS controllers are connected to mbigen hw module [1]. The mbigen module is probed with module_init, and, as such, is not guaranteed to probe before the SAS driver. So we need to support deferred probe. We check for probe deferral in the hw layer probe, so we not probe into the main layer and allocate shost, memories, etc., to later learn that we need to defer the probe. [1] ./Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt Signed-off-by:
-
- 29 Nov, 2016 1 commit
-
-
Dan Carpenter authored
There are some typos where we intended "<<" but have "<". Seems likely to cause a bunch of problems. Fixes: d3b688d3 ("scsi: hisi_sas: add v2 hw support for ECC and AXI bus fatal error") Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Acked-by:
-
- 25 Nov, 2016 8 commits
-
-
Xiang Chen authored
Add the function to set PHY min and max linkrate through sysfs interface. Signed-off-by:
-
John Garry authored
Sometimes the value of hisi_sas_device.running_req would go negative unless we have the check for running_req >= 0 before trying to decrement. This is because using running_req is not thread-safe. As such, the value for running_req may be actually incorrect, so use atomic64_t instead. Signed-off-by:
-
Xiang Chen authored
Check ERR bit of status to decide whether there is something wrong with initial register-D2H FIS. If error exists, PHY reset the channel to restart OOB. Signed-off-by:
-
Xiang Chen authored
Modify and add some SATA commands according to SATA protocol. Signed-off-by:
-
Xiang Chen authored
Delete repeated configuration items for hisi_sas_device() when we free a device. These items are now only set in hisi_sas_dev_gone(). Signed-off-by:
-
Xiang Chen authored
There are many BROADCAST primitives generated by the host. We are only interested in BROADCAST (CHANGE) primitives currently, so only process this. Signed-off-by:
-
Xiang Chen authored
Currently slots are allocated from queues in a round-robin fashion. This causes a problem for internal commands in device mode. For this mode, we should ensure that the internal abort command is the last command seen in the host for that device. We can only ensure this when we place the internal abort command after the preceding commands for device that in the same queue, as there is no order in which the host will select a queue to execute the next command. This queue restriction makes supporting scsi mq more tricky in the future, but should not be a blocker. Note: Even though v1 hw does not support internal abort, the allocation method is chosen to be the same for consistency. Signed-off-by: -
Xiang Chen authored
For ECC 1bit error, logic can recover it, so we only print a warning. For ECC multi-bit and AXI bus fatal error, we panic. Signed-off-by:
-
- 08 Nov, 2016 2 commits
-
-
John Garry authored
The hip06 D03 and hip07 D05 boards have different reference clock frequencies for the SAS controller. Register PHY_CTRL needs to be programmed differently according to this frequency, so add support for this. The default register setting in PHY_CTRL is for 50MHz, so only update this register when the refclk frequency is 66MHz. For ACPI we expect the _RST handler to set the correct value for PHY_CTRL (we're forced to take different approach for DT and ACPI as ACPI does not support fixed-clock device). Signed-off-by:
-
John Garry authored
Chipset hip07 incorporates v2 hw. Signed-off-by:
-
- 14 Sep, 2016 3 commits
-
-
John Garry authored
When the v2 hw is attached with many disks through an expander, there may be OOB reset resulting in a PHY going down after the speed is negotiated (very low probability). This issue is resolved by modifying the link control registers to send three identify frames before the PHY is ready (according to 6.10.3.3.2 in SAS 3.0 spec) and close ready when the PHY is down. Signed-off-by:
Hannes Reinecke <hare@suse.com> Signed-off-by:
-
John Garry authored
In setup_itct_v2_hw(), SATA device type SAS_SATA_PENDING is missing, so add it. Note: The HiSi SAS controller does not support SATA PM, so do not handle SAS_SATA_PM_PORT or SAS_SATA_PM. Signed-off-by:
-
John Garry authored
Function config_id_frame_v2_hw() is called twice for each PHY during initialisation, which is unneeded. So remove init_id_frame_v2_hw(), which only calls config_id_frame_v2_hw(). We will keep the call to config_id_frame_v2_hw() in start_phy_v2_hw() since it will be used for PHY reset functions. Signed-off-by:
-
