- 07 Feb, 2007 40 commits
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Kumar Gala authored
Added kprobes to ppc32 platforms that have use single_step_exception. This excludes 4xx and anything Book-E since their debug mechanisms for single stepping are completely different. Signed-off-by:Kumar Gala <galak@kernel.crashing.org>
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Paul Mackerras authored
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Paul Mackerras authored
H_BULK_REMOVE lets us remove 4 entries from the MMU hash table with one hypervisor call. This uses it in pSeries_lpar_hpte_invalidate so we can tear down mappings with fewer hypervisor calls. Signed-off-by:Paul Mackerras <paulus@samba.org>
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Paul Mackerras authored
Some instruction tracing tools use the RI (recoverable interrupt) bit in the MSR to indicate when it's safe to single-step. Currently we clear RI after restoring r13 when returning to userspace. However, if we single-step past the point where r13 is restored, we'll corrupt r13 in the exception entry code and not restore it. This moves the clearing of RI to just before r13 is restored so this doesn't happen. Signed-off-by: -
Livio Soares authored
To the issue: some point during 2.6.20 development, Paul Mackerras introduced the "lazy IRQ disabling" patch (very cool work, BTW). In that patch, the performance monitor unit exception was marked as "maskable", in the sense that if interrupts were soft-disabled, that exception could be ignored. This broke my PowerPC profiling code. The symptom that I see is that a varying number of interrupts (from 0 to $n$, typically closer to 0) get delivered, when, in reality, it should always be very close to $n$. The issue stems from the way masking is being done. Masking in this fashion seems to work well with the decrementer and external interrupts, because they are raised again until "really" handled. For the PMU, however, this does not apply (at least on my Xserver machine with a 970FX processor). If the PMU exception is not handled, it will _not_ be re-raised (at least on my machine). The documentation states that the PMXE bit in MMCR0 is set to 0 when the PMU exception is raised. However, software must re-set the bit to re-enable PMU exceptions. If the exception is ignored (as currently) not only is that interrupt lost, but because software does not re-set PMXE, the PMU registers are "frozen" forever. [This patch means that performance monitor exceptions are taken and handled even if irqs are off, as long as some other interrupt hasn't come along and caused interrupts to be hard-disabled. In this sense the PMU exception becomes like an NMI. The oprofile code for most powerpc processors does nothing that is unsafe in an NMI context, but the Cell oprofile code does a spin_lock_irqsave. However, that turns out to be OK because Cell doesn't actually use the performance monitor exception; performance monitor interrupts come in as a regular interrupt on Cell, so will be disabled when irqs are off. -- paulus.] Signed-off-by: -
David Gibson authored
The new dcr code does not currently compile when configured for native DCR access on ARCH=powerpc. This patch fixes the problems. Signed-off-by:
David Gibson <dwg@au1.ibm.com> Signed-off-by:
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Nathan Lynch authored
Some systems supported by the maple platform (e.g. JS2x blades running SLOF) are able to use the mmio_nvram backend for reading and writing nvram. This is an improvement over the current situation -- no nvram access from userspace at all. Select MMIO_NVRAM for the maple platform. Initialize the mmio_nvram backend from maple setup code. Signed-off-by:
Nathan Lynch <ntl@pobox.com> Signed-off-by:
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Olof Johansson authored
Base pasemi defconfig. Nothing special, just the native drivers plus common PCI-express/PCI cards. Signed-off-by:
Olof Johansson <olof@lixom.net> Signed-off-by:
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Olof Johansson authored
I/O TLB support for PA6T-1682M. Signed-off-by:
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Olof Johansson authored
The DMA controller on PWRficient is somewhat special -- has a PCI header so it looks like it's on the root PCI (-Express) root bus, but it uses more than the default number of interrupts (and they are hardwired). We need to wire up all interrupts for the DMA controller. The generic IRQ code will only map the primary interrupt from the PCI header (128), so add 129->211 by hand. Signed-off-by:
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Olof Johansson authored
Timebase update is simple on PA6T, since global updates can be done from one core by writing to an SPR. Signed-off-by:
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Olof Johansson authored
Implement reset on platforms/pasemi. Default is just to reset the cpu using the SDC registers. Signed-off-by:
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Olof Johansson authored
Powersave support on PA6T. Right now it only uses 'doze' mode, and will default to no savings (spin). Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
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Olof Johansson authored
Print out decoded machine check information on PA6T. Signed-off-by:
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Olof Johansson authored
Early debug output for PA Semi UART. Uses the 2.05 CI real mode ops. Signed-off-by:
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Pavel Roskin authored
G3 Blue & White is misconfigured by default so that CardBus controllers in PCI slots don't work. The PCI bridge is programmed to only allow access to bus 1 but not higher busses. The patch forces the PCI busses to be reassigned if a Grackle controller is found and the machine identifies itself as "PowerMac1,1" Signed-off-by:
Pavel Roskin <proski@gnu.org> Acked-by:
Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by:
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Ishizaki Kou authored
This patch creates defconfig file for Celleb platform. Signed-off-by:
Kou Ishizaki <kou.ishizaki@toshiba.co.jp> Acked-by:
Arnd Bergmann <arnd.bergmann@de.ibm.com> Signed-off-by:
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Ishizaki Kou authored
This patch adds base support for Celleb platform. Signed-off-by:
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Ishizaki Kou authored
SPU support routines for Celleb platform. Signed-off-by:
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Ishizaki Kou authored
Spu management ops in arch/platforms/cell/spu_priv1_mmio.h can be used commonly in of based platform. This patch separates spu management ops from native cell code and uses on celleb platform. Signed-off-by:
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Ishizaki Kou authored
This patch adds hypervisor console driver for Celleb platform. Signed-off-by:
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Ishizaki Kou authored
This patch adds udbg support for Celleb platform. Signed-off-by:
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Ishizaki Kou authored
Adds htab routines for Celleb platform. Signed-off-by:
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Ishizaki Kou authored
This patch creates Celleb platform dependent file to support iommu. Signed-off-by:
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Ishizaki Kou authored
USB host controller in SCC requires enable sequence. It should be done before USB host drivers start. Signed-off-by:
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Ishizaki Kou authored
This patch creates Celleb platform dependent files to support interrupts. Signed-off-by:
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Ishizaki Kou authored
This patch creates Celleb platform dependent files which add interfaces to call hypervisor. Signed-off-by:
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Jiri Kosina authored
arch/powerpc/platforms/powermac/smp.c::smp_core99_kick_cpu() contains local_irq_disable() call after local_irq_save(). This looks redundant. Signed-off-by:
Jiri Kosina <jkosina@suse.cz> Signed-off-by:
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Jiri Kosina authored
arch/powerpc/platforms/86xx/mpc86xx_smp.c::smp_86xx_kick_cpu() contains local_irq_disable() call after local_irq_save(). This looks redundant. Signed-off-by:
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Vitaly Bordug authored
Default config file for mpc8272ads (powerpc port).Though relevant bits went in, it is required to keep proper default configuration for the target, which seems to be missed initially. Signed-off-by:
Vitaly Bordug <vbordug@ru.mvista.com> Signed-off-by:
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Vitaly Bordug authored
Recent update of asm-powerpc/io.h caused cpm-related stuff to break in the current kernel. Current patch fixes it, as well as other inconsistencies expressed, that do not permit targets from working properly: - Updated dts with a chosen node with interrupt controller, - fixed messed device IDs among CPM2 SoC devices, - corrected odd header name and fixed type in defines, - Added 82xx subdir to the powerpc/platforms Makefile, missed during initial commit, - new solely-powerpc header file for 8260 family (was using one from arch/ppc, this one cleaned up from the extra stuff), in fact for now a placeholder to get the board-specific includes for stuff not yet capable to live with devicetree peeks only - Fixed couple of misprints in reference mpc8272 dts. Signed-off-by:
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Vitaly Bordug authored
This contains important fixes for the CPM2 PIC code. Eliminated CPM_IRQ_OFFSET, pulling the respective interrupt numbers from the interrupt mapping. Updated devicetree files to reflect that. Changed direct IC-related IO accesses to the IO accessors. Fixed all the sense values to keep coherency with ipic. In the current code, CPM2 stuff will have no IRQs and hence could be hardly usable. Signed-off-by:
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Geoff Levand authored
Update ps3_defconfig to enable USB mass storage and VFAT. Signed-off-by:
Geoff Levand <geoffrey.levand@am.sony.com> Acked-by:
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Geoff Levand authored
Add the missing pieces to support DMA scatter-gather on the PS3 system bus. Signed-off-by:
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Geoff Levand authored
Move the structures and routines needed for PS3 vuart port device registration to asm-powerpc/ps3.h. Signed-off-by:
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Geoff Levand authored
Move the PS3 system bus routines from drivers/ps3 to arch/powerpc/platforms/ps3. Signed-off-by:
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Robert P. J. Day authored
Add the inline function "is_power_of_2()" to log2.h, where the value zero is *not* considered to be a power of two. Signed-off-by:
Robert P. J. Day <rpjday@mindspring.com> Acked-by:
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Olof Johansson authored
Allow more than the default 256 MPIC sources. Allocates a new flag (MPIC_LARGE_VECTORS) to be used by platform code when instantiating the mpic. I picked 11 bits worth right now since it would cover the number of sources on any hardware I have seen. It can always be increased later if needed. Signed-off-by:
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Olof Johansson authored
Support for PA6T-style PMC registers. PMCs are completely implementation-dependent on PPC, and PA6T numbers them differently from the IBM model. Signed-off-by:
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Olof Johansson authored
Introduce _SYSDEV_ATTR(), to be used to just define the struct, and not a named variable with the attribute. Useful for arrays of sysdev_attributes. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
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