- 24 Apr, 2017 40 commits
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Adrian Hunter authored
The delay between tuning commands for SD cards is not part of the specification. A driver that needs it probably needs it for eMMC too, whereas most drivers would probably like to set it to 0. Make it a host member (host->tuning_delay) that defaults to the existing behaviour. Drivers can set it to zero to eliminate the delay, or set it to a positive value to always have a delay. Signed-off-by:
Adrian Hunter <adrian.hunter@intel.com> Signed-off-by:
Yangbo Lu <yangbo.lu@nxp.com> Signed-off-by:
Ulf Hansson <ulf.hansson@linaro.org>
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yangbo lu authored
eSDHC uses tuning block for tuning procedure. So the tuning block control register must be configured properly before tuning. Signed-off-by:
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yangbo lu authored
eSDHC supports signal voltage switch from 3.3v to 1.8v by eSDHC_PROCTL[VOLT_SEL] bit. This bit changes the value of output signal SDHC_VS, and there must be a control circuit out of eSDHC to change the signal voltage according to SDHC_VS output signal. Signed-off-by:
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yangbo lu authored
eSDHC could select peripheral clock or platform clock as clock source by the PCS bit of eSDHC Control Register, and this bit couldn't be reset by software reset for all. In default, the platform clock is used. But we have to use peripheral clock since it has a higher frequency to support eMMC HS200 mode and SD UHS-I mode. This patch is to add peripheral clock support and use it instead of platform clock if it's declared in eSDHC dts node. Signed-off-by:
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Adrian Hunter authored
The DSM used by some Intel controllers can return a 3 byte package. Allow for that by using memcpy to copy the bytes. Signed-off-by:
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Dan Carpenter authored
"dat" is a u64 and "shift" starts as 54 so this is a shift wrapping bug. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Jan Glauber authored
Add a pointer check to prevent this smatch warning: drivers/mmc/host/cavium.c:803 cvm_mmc_request() error: we previously assumed 'cmd->data' could be null (see line 782) This is a theoretical fix because MMC_CMD_ADTC seems to imply that cmd->data is not null. Nevertheless checking cmd->data before using it improves readability. Signed-off-by:
Jan Glauber <jglauber@cavium.com> Signed-off-by:
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Jan Glauber authored
Remove redundant mmc->card check reported by smatch: drivers/mmc/host/cavium.c:694 cvm_mmc_dma_request() warn: variable dereferenced before check 'mmc->card' (see line 675) Signed-off-by:
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Heiner Kallweit authored
So far a bounce buffer is used to serialize the scatterlist(s). This overhead can be avoided by switching to descriptor chain mode. As result the performance is drastically improved. On a Odroid-C2 with a 128 GB eMMC module raw reads reach 140 MB/s. Prerequisite for descriptor chain mode is that all scatterlist buffers are 8 byte aligned for 64-bit DMA. That's not always the case, at least the brcmfmac SDIO WiFi driver is known to cause problems. Therefore, for each request, check upfront whether all scatterlist buffers are 8 byte aligned and fall back to bounce buffer mode if that's not the case. Signed-off-by:
Heiner Kallweit <hkallweit1@gmail.com> Signed-off-by:
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Heiner Kallweit authored
This patch adds basic tuning which changes the rx clock phase only until a working setting is found. On a Odroid C2 with 128GB eMMC card and 200 MHz MMC clock only 180° rx clock phase make the system boot w/o CRC errors. With other MMC devices / clock speeds this might be different, therefore don't change the driver config in general. When retuning skip the currently active parameter set. This avoids the current problematic config to be chosen again if it causes CRC errors just occasionally. Signed-off-by:
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Heiner Kallweit authored
Introduce struct meson_tuning_params for storing the clock phase configurations. There's no functional change because tx and rx clock phase were implicitely set to CLK_PHASE_0 before. Signed-off-by:
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Winkler, Tomas authored
Annotate big endian values correctly and make sparse happy. In mmc_app_send_scr remove scr function parameter as it was updating card->raw_scr anyway. Signed-off-by:
Tomas Winkler <tomas.winkler@intel.com> Signed-off-by:
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Piotr Sroka authored
Add calling sdhci_get_of_property function to parse sdhci properties. Signed-off-by:
Piotr Sroka <piotrs@cadence.com> Acked-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Dan Carpenter authored
devm_pinctrl_get() returns error pointers, it never returns NULL. Fixes: 455e5cd6 ("mmc: omap_hsmmc: Pin remux workaround to support SDIO interrupt on AM335x") Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
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Hu Ziji authored
Add maintainer entry for Marvell Xenon eMMC/SD/SDIO Host Controller drivers. Signed-off-by:
Hu Ziji <huziji@marvell.com> Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Hu Ziji authored
Some SoCs have PHY PAD outside Xenon IP. PHY PAD voltage should match signalling voltage in use. Add generic SoC PHY PAD voltage control interface. Implement Aramda-3700 SoC PHY PAD voltage control. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Hu Ziji authored
Marvell Xenon eMMC/SD/SDIO Host Controller contains PHY. Multiple types of PHYs are supported. Add support to multiple types of PHYs init and configuration. Add register definitions of PHYs. Xenon PHY cannot fit in kernel common PHY framework. Xenon SDHC PHY register is a part of Xenon SDHC register set. Besides, MMC initialization has to call several PHY functions to complete timing setting. Those PHY setting functions have to access SDHC registers and know current MMC setting, such as bus width, clock frequency and speed mode. As a result, implement Xenon PHY in MMC host directory. Signed-off-by:
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Hu Ziji authored
Add Xenon eMMC/SD/SDIO host controller core functionality. Add Xenon specific initialization process. Add Xenon specific mmc_host_ops APIs. Add Xenon specific register definitions. Add CONFIG_MMC_SDHCI_XENON support in drivers/mmc/host/Kconfig. Marvell Xenon SDHC conforms to SD Physical Layer Specification Version 3.01 and is designed according to the guidelines provided in the SD Host Controller Standard Specification Version 3.00. Signed-off-by:
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Hu Ziji authored
Marvell Xenon SDHC can support eMMC/SD/SDIO. Add Xenon-specific properties. Also add properties for Xenon PHY setting. Signed-off-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Hu Ziji authored
Export sdhci_enable_sdio_irq() from sdhci.c. Thus vendor SDHC driver can implement its specific SDIO irq control. Signed-off-by:
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Hu Ziji authored
Export sdhci_start_signal_voltage_switch() from sdhci.c. Thus vendor sdhci driver can implement its own signal voltage switch routine. Signed-off-by:
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Hu Ziji authored
Export sdhci_set_ios() in sdhci.c. Thus vendor sdhci driver can implement its own set_ios() routine. Signed-off-by:
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Gregory CLEMENT authored
First version of the binding didn't have the eMMC clock. This patch allows to not registering the eMMC clock if it is not present in the device tree. Then the device tree can be backwards compatible. Suggested-by:
Stephen Boyd <sboyd@codeaurora.org> Signed-off-by:
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Konstantin Porotchkin authored
Add fixed clock of 400MHz to system controller driver. This clock is used as SD/eMMC clock source. Signed-off-by:
Konstantin Porotchkin <kostap@marvell.com> Reviewed-by:
Omri Itach <omrii@marvell.com> Reviewed-by:
Hanna Hawa <hannah@marvell.com> [fixed up conflicts, added error handling --rmk] Signed-off-by:
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Jan Glauber authored
Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
Steven J. Hill <steven.hill@cavium.com> Signed-off-by:
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Jan Glauber authored
Add support for switching to DDR mode for eMMC devices. Signed-off-by:
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Jan Glauber authored
Add Support for the scatter-gather DMA available in the ThunderX MMC units. Up to 16 DMA requests can be processed together. Signed-off-by:
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Jan Glauber authored
Add a platform driver for ThunderX ARM SOCs. Signed-off-by:
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Jan Glauber authored
This core driver will be used by a MIPS platform driver or by an ARM64 PCI driver. The core driver implements the mmc_host_ops and slot probe & remove functions. Callbacks are provided to allow platform specific interrupt enable and bus locking. The host controller supports: - up to 4 slots that can contain sd-cards or eMMC chips - 1, 4 and 8 bit bus width - SDR and DDR - transfers up to 52 Mhz (might be less when multiple slots are used) - DMA read/write - multi-block read/write (but not stream mode) Voltage is limited to 3.3v and shared for all slots (vmmc and vmmcq). A global lock for all MMC devices is required because the host controller is shared. Signed-off-by:
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Jan Glauber authored
Add description of Cavium Octeon and ThunderX SOC device tree bindings. CC: Ulf Hansson <ulf.hansson@linaro.org> CC: Rob Herring <robh+dt@kernel.org> CC: Mark Rutland <mark.rutland@arm.com> CC: devicetree@vger.kernel.org Signed-off-by:
Rob Herring <robh+dt@kernel.org> Signed-off-by:
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Linus Walleij authored
We have this construction: if (a && b && !c) finalize; else block; finalize; Which is equivalent by boolean logic to: if (!a || !b || c) block; finalize; Which is simpler code. Reviewed-by:
Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Linus Walleij authored
mmc_wait_for_data_req_done() is called in exactly one place, and having it spread out is making things hard to oversee. Factor this function into mmc_finalize_areq(). Reviewed-by:
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Linus Walleij authored
"previous" is a better name for the variable storing the previous asynchronous request, better than the opaque name "data" atleast. We see that we assign the return status to the returned variable on all code paths, so we might as well just do that immediately after calling mmc_finalize_areq(). Reviewed-by:
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Adrian Hunter authored
In preparation to reuse the code for CQE support. Signed-off-by:
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Adrian Hunter authored
In preparation to reuse the code for CQE support. Signed-off-by:
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Adrian Hunter authored
Factor out data preparation into a separate function mmc_blk_data_prep() which can be re-used for command queuing. Signed-off-by:
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Adrian Hunter authored
mmc_apply_rel_rw() will be used by Software Command Queuing also. In that case the command argument is not the block address so change mmc_apply_rel_rw() to get block address from the request. Signed-off-by:
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Adrian Hunter authored
RPMB does not allow Command Queue commands. Disable and re-enable the Command Queue when switching. Note that the driver only switches partitions when the queue is empty. Signed-off-by:
Harjani Ritesh <riteshh@codeaurora.org> Reviewed-by:
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Adrian Hunter authored
Normal read and write commands may not be used while the command queue is enabled. Disable the Command Queue when mmc_test is probed and re-enable it when it is removed. Signed-off-by:
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Adrian Hunter authored
Add helper functions to enable or disable the Command Queue. Signed-off-by:
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