No code changes in this patch, just cleanup and version bump.

* e1000_irq_disable was used to disable irqs which called
  synchronize_irq which in turn caused a solid hang on SMP
  systems.

* Bug fix: TSO s/w workaround for premature desc write-back by h/w.  h/w
  was indicating desc done before DMA is complete, causing resources to
  be returned to OS too early.  Bad things happen then.
* Bug fix: Not time-stamping descriptors for fragmented sends.  Could 
  cause false hang-detection.
* Removed unecessary #ifdefs

rather than large static allocation on the stack

in tg3_enable_ints.

The bcm570x chips provide a register that disables (masks) or enables
interrupts, and as a side effect, each write to this register regardless 
of value clears various PCI and internal interrupt-pending flags.  This
register, intr-mbox-0, provides a superset of the function provided
by the mask-pci-int and clear-pci-int bits in the misc-host-ctrl register.

Furthermore, the documentation clearly implies use of this register,
as an indicator that the host [tg3 driver] is in its interrupt handler.

The new tg3 logic, taking this knowledge into account, masks-and-clears
irqs using intr-mbox-0 [only] when a hard irq is received, and
unmasks-and-clears irqs at the end of tg3_poll after all NAPI events
have been exhausted.

The old logic twiddled the misc-host-ctrl irq masking bits separately
from intr-mbox-0 bits, which was not only inconsistent but also
a few additional I/Os that were not needed.

The tg3_timer one is very likely superfluous, and will hopefully be
removed after extended testing.

* Removed /proc/net/PRO_LAN_Adapters
* Added ethtool GSTATS support

* Bug Fix: TCO workaround after hard reset of controller to wait for TCO
  traffic to settle.  Workaround requires issuing a CU load base command
  after hard reset, followed by a wait for scb and finally a wait for
  TCO traffic bit to clear.  Affects 82559s and above wired to SMBus.

into home.transmeta.com:/home/torvalds/v2.5/linux

__virt_to_bus/__bus_to_virt depended on INTEGRATOR_HDR0_SDRAM_BASE
Unfortunately, this is defined in arch-integrator/platform.h, and
we really don't want to include it in memory.h.

We instead use BUS_OFFSET, which will eventually depend on the CPU
number in the system.

Only default BLK_DEV_IDEDMA on BLK_DEV_IDEDMA_ICS if ARCH_ACORN is
set, not if ARM is set.  There are PCI ARM systems out there!

Ensure that we clean up properly after initialisation error,
releasing all claimed resources in an orderly manner and
returning the correct error code.

Add cfbfillrect / cfbcopyarea / cfbimgblt objects for SA1100fb.
Remove redundant "pm" member.

Found a buglet in the marvel code -- doesn't change the number of IRQS
just the logic to get there.. This applies on top of the other marvel
code.

/jeff

into kanga.twiddle.net:/home/rth/linux/axp-2.5

to header files where they belong.

of AGP and SRMCONS patches.

From Jeff.Wiedemeier@hp.com.