- 08 Jun, 2019 14 commits
-
-
Vladimir Oltean authored
This will be used to keep state for RX timestamping. It is global because the switch serializes timestampable and meta frames when trapping them towards the CPU port (lower port indices have higher priority) and therefore having one state machine per port would create unnecessary complications. Signed-off-by:
Vladimir Oltean <olteanv@gmail.com> Signed-off-by:
David S. Miller <davem@davemloft.net>
-
Vladimir Oltean authored
This adds support in the tagger for understanding the source port and switch id of meta frames. Their timestamp is also extracted but not used yet - this needs to be done in a state machine that modifies the previously received timestampable frame - will be added in a follow-up patch. Also take the opportunity to: - Remove a comment in sja1105_filter made obsolete by e8d67fa5 ("net: dsa: sja1105: Don't store frame type in skb->cb") - Reorder the checks in sja1105_filter to optimize for the most likely scenario first: regular traffic. Signed-off-by:
-
Vladimir Oltean authored
Although meta frames are configured to be sent at SJA1105_META_DMAC (01-80-C2-00-00-0E) which is a multicast MAC address that would also be trapped by the switch to the CPU, were it to receive it on a front-panel port, meta frames are conceptually not link-local frames, they only carry their RX timestamps. The choice of sending meta frames at a multicast DMAC is a pragmatic one, to avoid installing an extra entry to the DSA master port's multicast MAC filter. Signed-off-by:
-
Vladimir Oltean authored
This table is used to program the switch to emit "meta" follow-up Ethernet frames (which contain partial RX timestamps) after each link-local frame that was trapped to the CPU port through MAC filtering. This includes PTP frames. Signed-off-by:
-
Vladimir Oltean authored
Meta frames are sent on the CPU port by the switch if RX timestamping is enabled. They contain a partial timestamp of the previous frame. They are Ethernet frames with the Ethernet header constructed out of: - SJA1105_META_DMAC - SJA1105_META_SMAC - ETH_P_SJA1105_META The Ethernet payload will be decoded in a follow-up patch. Signed-off-by:
Florian Fainelli <f.fainelli@gmail.com> Signed-off-by:
-
Vladimir Oltean authored
On TX, timestamping is performed synchronously from the port_deferred_xmit worker thread. In management routes, the switch is requested to take egress timestamps (again partial), which are reconstructed and appended to a clone of the skb that was just sent. The cloning is done by DSA and we retrieve the pointer from the structure that DSA keeps in skb->cb. Then these clones are enqueued to the socket's error queue for application-level processing. Signed-off-by:
-
Vladimir Oltean authored
The design of this PHC driver is influenced by the switch's behavior w.r.t. timestamping. It exposes two PTP counters, one free-running (PTPTSCLK) and the other offset- and frequency-corrected in hardware through PTPCLKVAL, PTPCLKADD and PTPCLKRATE. The MACs can sample either of these for frame timestamps. However, the user manual warns that taking timestamps based on the corrected clock is less than useful, as the switch can deliver corrupted timestamps in a variety of circumstances. Therefore, this PHC uses the free-running PTPTSCLK together with a timecounter/cyclecounter structure that translates it into a software time domain. Thus, the settime/adjtime and adjfine callbacks are hardware no-ops. The timestamps (introduced in a further patch) will also be translated to the correct time domain before being handed over to the userspace PTP stack. The introduction of a second set of PHC operations that operate on the hardware PTPCLKVAL/PTPCLKADD/PTPCLKRATE in the future is somewhat unavoidable, as the TTEthernet core uses the corrected PTP time domain. However, the free-running counter + timecounter structure combination will suffice for now, as the resulting timestamps yield a sub-50 ns synchronization offset in steady state using linuxptp. For this patch, in absence of frame timestamping, the operations of the switch PHC were tested by syncing it to the system time as a local slave clock with: phc2sys -s CLOCK_REALTIME -c swp2 -O 0 -m -S 0.01 Signed-off-by:
-
Vladimir Oltean authored
These are needed for the situation where the switch driver and the PTP driver are both built as modules. Signed-off-by:
-
Vladimir Oltean authored
The incl_srcpt setting makes the switch mangle the destination MACs of multicast frames trapped to the CPU - a primitive tagging mechanism that works even when we cannot use the 802.1Q software features. The downside is that the two multicast MAC addresses that the switch traps for L2 PTP (01-80-C2-00-00-0E and 01-1B-19-00-00-00) quickly turn into a lot more, as the switch encodes the source port and switch id into bytes 3 and 4 of the MAC. The resulting range of MAC addresses would need to be installed manually into the DSA master port's multicast MAC filter, and even then, most devices might not have a large enough MAC filtering table. As a result, only limit use of incl_srcpt to when it's strictly necessary: when under a VLAN filtering bridge. This fixes PTP in non-bridged mode (standalone ports). Otherwise, PTP frames, as well as metadata follow-up frames holding RX timestamps won't be received because they will be blocked by the master port's MAC filter. Linuxptp doesn't help, because it only requests the addition of the unmodified PTP MACs to the multicast filter. This issue is not seen in bridged mode because the master port is put in promiscuous mode when the slave ports are enslaved to a bridge. Therefore, there is no downside to having the incl_srcpt mechanism active there. Signed-off-by:
-
Vladimir Oltean authored
>From reading the P/Q/R/S user manual, it appears that TPID is used by the switch for detecting S-tags and TPID2 for C-tags. Their meaning is not clear from the E/T manual. Signed-off-by:
-
Vladimir Oltean authored
This is a cosmetic patch, pre-cursor to making another change to the General Parameters Table (incl_srcpt) which does not logically pertain to the sja1105_change_tpid function name, but not putting it there would otherwise create a need of resetting the switch twice. So simply move the existing code into the .port_vlan_filtering callback, where the incl_srcpt change will be added as well. Signed-off-by:
-
Vladimir Oltean authored
This removes the existing implementation from tag_sja1105, which was partially incorrect (it was not changing the MAC header offset, thereby leaving it to point 4 bytes earlier than it should have). This overwrites the VLAN tag by moving the Ethernet source and destination MACs 4 bytes to the right. Then skb->data (assumed to be pointing immediately after the EtherType) is temporarily pushed to the beginning of the new Ethernet header, the new Ethernet header offset and length are recorded, then skb->data is moved back to where it was. Signed-off-by:
-
Vladimir Oltean authored
This is helpful for e.g. draining per-driver (not per-port) tagger queues. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> Reviewed-by:
-
Vladimir Oltean authored
For drivers that use deferred_xmit for PTP frames (such as sja1105), there is no need to perform matching between PTP frames and their egress timestamps, since the sending process can be serialized. In that case, it makes sense to have the pointer to the skb clone that DSA made directly in the skb->cb. It will be used for pushing the egress timestamp back in the application socket's error queue. Signed-off-by:
-
- 07 Jun, 2019 4 commits
-
-
git://git.kernel.org/pub/scm/linux/kernel/git/davem/netDavid S. Miller authored
Some ISDN files that got removed in net-next had some changes done in mainline, take the removals. Signed-off-by: -
git://git.kernel.org/pub/scm/linux/kernel/git/davem/netLinus Torvalds authored
Pull networking fixes from David Miller: 1) Free AF_PACKET po->rollover properly, from Willem de Bruijn. 2) Read SFP eeprom in max 16 byte increments to avoid problems with some SFP modules, from Russell King. 3) Fix UDP socket lookup wrt. VRF, from Tim Beale. 4) Handle route invalidation properly in s390 qeth driver, from Julian Wiedmann. 5) Memory leak on unload in RDS, from Zhu Yanjun. 6) sctp_process_init leak, from Neil HOrman. 7) Fix fib_rules rule insertion semantic change that broke Android, from Hangbin Liu. * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net: (33 commits) pktgen: do not sleep with the thread lock held. net: mvpp2: Use strscpy to handle stat strings net: rds: fix memory leak in rds_ib_flush_mr_pool ipv6: fix EFAULT on sendto with icmpv6 and hdrincl ipv6: use READ_ONCE() for inet->hdrincl as in ipv4 Revert "fib_rules: return 0 directly if an exactly same rule exists when NLM_F_EXCL not supplied" net: aquantia: fix wol configuration not applied sometimes ethtool: fix potential userspace buffer overflow Fix memory leak in sctp_process_init net: rds: fix memory leak when unload rds_rdma ipv6: fix the check before getting the cookie in rt6_get_cookie ipv4: not do cache for local delivery if bc_forwarding is enabled s390/qeth: handle error when updating TX queue count s390/qeth: fix VLAN attribute in bridge_hostnotify udev event s390/qeth: check dst entry before use s390/qeth: handle limited IPv4 broadcast in L3 TX path net: fix indirect calls helpers for ptype list hooks. net: ipvlan: Fix ipvlan device tso disabled while NETIF_F_IP_CSUM is set udp: only choose unbound UDP socket for multicast when not in a VRF net/tls: replace the sleeping lock around RX resync with a bit lock ... -
git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdmaLinus Torvalds authored
Pull rdma fixes from Jason Gunthorpe: "Things are looking pretty quiet here in RDMA, not too many bug fixes rolling in right now. The usual driver bug fixes and fixes for a couple of regressions introduced in 5.2: - Fix a race on bootup with RDMA device renaming and srp. SRP also needs to rename its internal sys files - Fix a memory leak in hns - Don't leak resources in efa on certain error unwinds - Don't panic in certain error unwinds in ib_register_device - Various small user visible bug fix patches for the hfi and efa drivers - Fix the 32 bit compilation break" * tag 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma: RDMA/efa: Remove MAYEXEC flag check from mmap flow mlx5: avoid 64-bit division IB/hfi1: Validate page aligned for a given virtual address IB/{qib, hfi1, rdmavt}: Correct ibv_devinfo max_mr value IB/hfi1: Insure freeze_work work_struct is canceled on shutdown IB/rdmavt: Fix alloc_qpn() WARN_ON() RDMA/core: Fix panic when port_data isn't initialized RDMA/uverbs: Pass udata on uverbs error unwind RDMA/core: Clear out the udata before error unwind RDMA/hns: Fix PD memory leak for internal allocation RDMA/srp: Rename SRP sysfs name after IB device rename trigger -
git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linuxLinus Torvalds authored
Pull arm64 fixes from Will Deacon: "Another round of mostly-benign fixes, the exception being a boot crash on SVE2-capable CPUs (although I don't know where you'd find such a thing, so maybe it's benign too). We're in the process of resolving some big-endian ptrace breakage, so I'll probably have some more for you next week. Summary: - Fix boot crash on platforms with SVE2 due to missing register encoding - Fix architected timer accessors when CONFIG_OPTIMIZE_INLINING=y - Move cpu_logical_map into smp.h for use by upcoming irqchip drivers - Trivial typo fix in comment - Disable some useless, noisy warnings from GCC 9" * tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: arm64: Silence gcc warnings about arch ABI drift ARM64: trivial: s/TIF_SECOMP/TIF_SECCOMP/ comment typo fix arm64: arch_timer: mark functions as __always_inline arm64: smp: Moved cpu_logical_map[] to smp.h arm64: cpufeature: Fix missing ZFR0 in __read_sysreg_by_encoding()
-
- 06 Jun, 2019 22 commits
-
-
David S. Miller authored
Robert Hancock says: ==================== Xilinx axienet driver updates (v5) This is a series of enhancements and bug fixes in order to get the mainline version of this driver into a more generally usable state, including on x86 or ARM platforms. It also converts the driver to use the phylink API in order to provide support for SFP modules. Changes since v4: -Use reverse christmas tree variable order ==================== Signed-off-by: -
Robert Hancock authored
Convert this driver to use the phylink API rather than the legacy PHY API. This allows for better support for SFP modules connected using a 1000BaseX or SGMII interface. Signed-off-by:
Robert Hancock <hancock@sedsystems.ca> Signed-off-by:
-
Robert Hancock authored
Currently the axienet driver requires the use of a second devicetree node, referenced by an axistream-connected attribute on the Ethernet device node, which contains the resources for the AXI DMA block used by the device. This setup is problematic for a use case we have where the Ethernet and DMA cores are behind a PCIe to AXI bridge and the memory resources for the nodes are injected into the platform devices using the multifunction device subsystem - it's not easily possible for the driver to obtain the platform-level resources from the linked device. In order to simplify that usage model, and simplify the overall use of this driver in general, allow for all of the resources to be kept on one node where the resources are retrieved using platform device APIs rather than device-tree-specific ones. The previous usage setup is still supported if the axistream-connected attribute is specified. Signed-off-by:
-
Robert Hancock authored
The axienet driver requires the use of an axistream-connected attribute, but this isn't documented in the devicetree bindings. Document how this attribute is supposed to be used, including the upcoming change to make the usage of this attribute optional. Signed-off-by:
-
Robert Hancock authored
This driver was previously using the parent node of the specified PHY node as the device node to register the MDIO bus on. Andrew Lunn pointed out this is wrong as the PHY node is potentially not even underneath the MDIO bus for the current device instance. Find the MDIO node explicitly by looking it up by name under the controller's device node instead. This could potentially break existing device trees if they don't use "mdio" as the name for the MDIO bus, but I did not find any with various searches and Xilinx's examples all use mdio as the name so it seems like this should be relatively safe. Signed-off-by:
-
Robert Hancock authored
The mdio child node for the MDIO bus is generally required when using this driver but was not documented other than being shown in the example. Document it as an optional (but usually required) parameter. Signed-off-by:
-
Robert Hancock authored
On some platforms, such as iMX6 with PCIe devices, crashes or hangs can occur if the axienet device continues to perform DMA transfers after parent devices/busses have been shut down. Shut down the axienet interface during its shutdown callback in order to avoid this. Signed-off-by:
-
Robert Hancock authored
Failing initialization on a missing MAC address property is excessive. We can just fall back to using a random MAC instead, which at least leaves the interface in a functioning state. Signed-off-by:
-
Robert Hancock authored
It is possible that the interrupt handler fires and frees up space in the TX ring in between checking for sufficient TX ring space and stopping the TX queue in axienet_start_xmit. If this happens, the queue wake from the interrupt handler will occur before the queue is stopped, causing a lost wakeup and the adapter's transmit hanging. To avoid this, after stopping the queue, check again whether there is sufficient space in the TX ring. If so, wake up the queue again. Signed-off-by:
-
Robert Hancock authored
Previously this driver only handled interrupts from the DMA RX and TX blocks, not from the Ethernet core itself. Add optional support for the Ethernet core interrupt, which is used to detect rx_missed and framing errors signalled by the hardware. In order to use this interrupt, a third interrupt needs to be specified in the device tree. Signed-off-by:
-
Robert Hancock authored
Specify IRQF_SHARED to support shared interrupts. If the interrupt handler is called and the device is not indicating an interrupt, just return IRQ_NONE rather than spewing error messages. Signed-off-by:
-
Robert Hancock authored
These registers are important for troubleshooting the state of the DMA cores. Signed-off-by:
-
Robert Hancock authored
Add support for setting the RX and TX ring sizes for this driver using ethtool. Also increase the default RX ring size as the previous default was far too low for good performance in some configurations. Signed-off-by:
-
Robert Hancock authored
The Xilinx DMA blocks each have their own reset register, but they both reset the entire DMA engine, so only one of them needs to be reset. Also, when stopping the device, we need to not just command the DMA blocks to stop, but wait for them to stop, and trigger a device reset to ensure that they are completely stopped. Signed-off-by:
-
Robert Hancock authored
The MDIO clock divisor register setting was only applied on the initial startup when the driver was loaded. However, this setting is cleared when the device is reset, such as would occur when the interface was taken down and brought up again, and so the MDIO bus would be non-functional afterwards. Split up the MDIO bus setup and enable into separate functions and re-enable the bus after a device reset, to ensure that the MDIO registers are set properly. This also allows us to remove direct access to MDIO registers in xilinx_axienet_main.c and centralize them all in xilinx_axienet_mdio.c. Also, lock the MDIO bus lock around the device reset process, to avoid MDIO accesses from occurring while the MDIO is disabled during the reset. Signed-off-by:
-
Robert Hancock authored
Since the MDIO is is brought up before the netdev is registered, it should be torn down after the netdev is removed. Otherwise, PHY accesses can potentially access freed MDIO bus references and cause a crash. Signed-off-by:
-
Robert Hancock authored
This driver was previously always calculating the MDIO clock divisor (from AXI bus clock to MDIO bus clock) based on the CPU clock frequency, assuming that it is the same as the AXI bus frequency, but that simplistic method only works on the MicroBlaze platform. Add support for specifying the clock used for the device in the device tree using the clock framework. If the clock is specified then it will be used when calculating the clock divisor. The previous CPU clock detection method is left for backward compatibility if no clock is specified. Signed-off-by:
-
Robert Hancock authored
This driver should now build on (at least) X86 and ARM platforms, so add them as supported platforms for the driver in Kconfig. Signed-off-by:
-
Robert Hancock authored
The MDIO bus for this driver was being named using the result of of_address_to_resource on a node which may not have any resource on it, but the return value of that call was not checked so it was using some random value in the bus name. Change to name the MDIO bus based on the resource start of the actual Ethernet register block. Signed-off-by:
-
Robert Hancock authored
This driver was using in_be32 and out_be32 IO accessors which do not exist on most platforms. Also, the use of big-endian accessors does not seem correct as this hardware is accessed over an AXI bus which, to the extent it has an endian-ness, is little-endian. Switch to standard ioread32/iowrite32 accessors. Signed-off-by:
-
Robert Hancock authored
This driver was casting skb pointers to u32 and storing them as such in the DMA buffer descriptor, which is obviously broken on 64-bit. The area of the buffer descriptor being used is not accessed by the hardware and has sufficient room for a 32 or 64-bit pointer, so just store the skb pointer as such. Signed-off-by:
-
Dinh Nguyen authored
On the Arria10, Agilex, and Stratix10 SoC, there are a few differences from the Cyclone5 and Arria5: - The emac PHY setup bits are in separate registers. - The PTP reference clock select mask is different. - The register to enable the emac signal from FPGA is different. Thus, this patch creates a separate function for setting the phy modes on Arria10/Agilex/Stratix10. The separation is based a new DTS binding: "altr,socfpga-stmmac-a10-s10". Signed-off-by:
Dinh Nguyen <dinguyen@kernel.org> Signed-off-by:
-
