- 21 Jun, 2019 40 commits
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Leo Liu authored
No UVDW tile any more from VCN2.0, so mark out related fields. It fixes error: "[drm] Register(0) [mmUVD_PGFSM_STATUS] failed to reach value 0x002aaaaa != 0x00aaaaaa" Signed-off-by:
Leo Liu <leo.liu@amd.com> Acked-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Kenneth Feng authored
Enable uclk dpm on navi10 as the result of removing fast switch setting. Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Kenneth Feng authored
PPSMC_MSG_SetUclkFastSwitch message can be applied on vega20, but can't on navi10. This is the prerequisite of uclk dpm on navi10. Signed-off-by:
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Xiaojie Yuan authored
gfx_v10_0_kiq_enable_kgq() is called only when async_gfx_ring is enabled, so should gfx_v10_0_kiq_disable_kgq(). Signed-off-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Acked-by:
Jack Xiao <Jack.Xiao@amd.com> Signed-off-by:
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Xiaojie Yuan authored
we already selected se/sh at the beginning of the for loop Signed-off-by:
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Jack Xiao authored
It enables MES FW backdoor loading in ip block functions. Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
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Jack Xiao authored
After MES firmware gets loaded, it enables MES engine starting execution. Signed-off-by:
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Jack Xiao authored
It implements MES firmware backdoor loading. Signed-off-by:
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Jack Xiao authored
Free ucode GPU buffers. Signed-off-by:
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Jack Xiao authored
Allocate GPU buffer and upload mes data ucode to the buffer. Signed-off-by:
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Jack Xiao authored
Allocate GPU buffer and upload ucode firmware to the buffer. Signed-off-by:
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Jack Xiao authored
It implements the CPU buffer destruction of ucode. Signed-off-by:
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Jack Xiao authored
It requests MES firmware binary and uploads to CPU buffer. Signed-off-by:
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Jack Xiao authored
The newly added fields is to store mes firmware related information. Signed-off-by:
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Jack Xiao authored
The newly added firmware struct is for mes firmware file. Signed-off-by:
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Jack Xiao authored
MES requires two seperate firmwares: ucode and ucode data. Signed-off-by:
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Jack Xiao authored
Incorrect programming with 64bit gpu address assignment for 32bit variable. Signed-off-by:
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tiancyin authored
[why] When page fault happens, it could lead to sdma hang is RESP_MODE = 0 for non-PRT case. [how] Setting SDMAx_UTCL1_CNTL.RESP_MODE to 0b011 to avoid SDMA halt. Reviewed-by:
tiancyin <tianci.yin@amd.com> Signed-off-by:
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Hawking Zhang authored
It's not needed for navi. v2: remove unused variable (Alex) Signed-off-by:
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Jack Xiao authored
Enable VCN power gating by default. Signed-off-by:
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Jack Xiao authored
On navi1x, vcn dpm scheme was merged into powergating scheme. Signed-off-by:
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Jack Xiao authored
It will cause bus hang to access register UVD_STATUS when VCN is in the state of power gated. Signed-off-by:
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Kenneth Feng authored
add new interface for vcn powrergating and vcn dpm as well. Signed-off-by:
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Kenneth Feng authored
enable vcn powergating in driver for navi10 v2: set vcn pg bit according to AMD_PG_SUPPORT_VCN flag Signed-off-by:
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Jack Xiao authored
For sw control power gating, it needs notify SMU to power up/down VCN when enter/exit working state. Signed-off-by:
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Jack Xiao authored
1). use PREEMPT_QUEUE instead of RESET_QUEUE for gfx ring disablement. 2). Need wait for unmapping queue done before continue execution. Signed-off-by:
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Huang Rui authored
This patch sets dpm_enabled flag but don't enable vcn dpm, because vcn dpm doesn't work so far and we needs to enable the sysfs interfaces. Signed-off-by:
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Kenneth Feng authored
update the smu11_driver_if_navi10.h since navi10 smu fw update to 42.15.0 Signed-off-by:
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Xiaojie Yuan authored
'adev->in_suspend' code path is missing in gfx_v10_0_gfx_init_queue() Signed-off-by:
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Tianci Yin authored
temporarily disable to avoid s3 test failure. s3 test failure log: "[drm:amdgpu_job_timedout [amdgpu]] *ERROR* ring sdma0 timeout, signaled seq=8278, emitted seq=8281" Reviewed-by:
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Tianci Yin authored
add new registers: mmCGTT_SPI_CLK_CTRL, mmDB_DEBUG3 and mmGL2C_CGTT_SCLK_CTRL. Reviewed-by:
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Huang Rui authored
This dpm_enabled flag will be recognized as the VCN DPM enabled as well. In fact VCN/DCN DPM on Navi10 is not good so far, so we cannot enable it for now. Signed-off-by:
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Kenneth Feng authored
This patch is to fix the incorrect type of pptable, otherwise, the data will be totally wrong in parsing phase. Signed-off-by:
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Huang Rui authored
This header is actually for each asic, so we should not include in smu_v11_0.c. And rename the one for navi10. v2: add hack for XGMI (Alex) Signed-off-by:
Kevin Wang <kevin1.wang@amd.com> Reviewed-by:
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Huang Rui authored
Getting MAX_FAN_RPM value needs to be read by pptable, so it should be moved to asic level. Signed-off-by:
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Huang Rui authored
This patch introduces new smu power source type, it's to handle the different AC/DC source defines for each asic with the same smu ip. Signed-off-by:
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Huang Rui authored
This patch moves the rest of Watermarks_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by:
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Huang Rui authored
This patch moves the rest of SmuMetrics_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by:
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Huang Rui authored
This patch moves the rest of PPTable_t uses into asic level. It's to avoid the conflicts with different asic. Signed-off-by:
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Huang Rui authored
This patch uses the table size member in the structure instead of getting directly, because the table is different in each asic. Signed-off-by:
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