- 22 Jan, 2014 40 commits
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Felix Fietkau authored
Only one MIPS development board actually supports enabling/disabling DMA coherency at runtime, so it's not a good idea to push the overhead of checking that configuration setting onto every other supported target as well. Signed-off-by:
Felix Fietkau <nbd@openwrt.org> Signed-off-by:
John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/5912/
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Steven J. Hill authored
Clean-up code according to the 'checkpatch.pl' script. Signed-off-by:
Steven J. Hill <Steven.Hill@imgtec.com> Reviewed-by:
Qais Yousef <Qais.Yousef@imgtec.com> Patchwork: http://patchwork.linux-mips.org/patch/6097/Reviewed-by:
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Deng-Cheng Zhu authored
Malta with multi-core CM platforms can now use APRP functionality. Signed-off-by:
Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Signed-off-by:
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Deng-Cheng Zhu authored
This patch adds RTLX API support for platforms having a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
Split the RTLX functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
This patch adds VPE loader support for platforms having a CMP. Signed-off-by:
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Deng-Cheng Zhu authored
Split the VPE functionality in preparation for adding support for CMP platforms. Common functions remain in the original file and a new file contains code specific to platforms that do not have a CMP present. Signed-off-by:
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Steven J. Hill authored
This patch accomplishes the following: * Clean up wording on all MIPS MT configuration menu items. * Simplify and neaten up options selected by MIPS_MT_SMP. * Make MIPS_MT_SMTC support as deprecated. * Make MIPS_CMP support to depend on MIPS_MT_SMP also. * Remove redundant options selected by MIPS_CMP. Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
Leonid Yegoshin <Leonid.Yegoshin@imgtec.com> Signed-off-by:
Markos Chandras <markos.chandras@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
The interAptiv is a power-efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The interAptiv combines a multi-threading pipeline with a coherence manager to deliver improved computational throughput and power efficiency. The interAptiv can contain one to four MIPS32R3 interAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by:
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Leonid Yegoshin authored
Add processor identifiers for UP and MT interAptiv processors. Signed-off-by:
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Steven J. Hill authored
Add a new mips/segments debugfs file to print the 6 segmentation control registers for supported cores. A sample from a proAptiv core is given below: Signed-off-by:
James Hogan <james.hogan@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
The Fixed Page Size TLB (FTLB) is a set-associative dual entry TLB. Its purpose is to reduce the number of TLB misses by increasing the effective TLB size and keep the implementation complexity to minimum levels. A supported core can have both VTLB and FTLB. Reviewed-by:
Paul Burton <paul.burton@imgtec.com> Signed-off-by:
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Leonid Yegoshin authored
The TLBINVF instruction can be used to flush the entire VTLB. This eliminates the need for the TLBWI loop and improves performance. Reviewed-by:
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Leonid Yegoshin authored
Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
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Leonid Yegoshin authored
The proAptiv Multiprocessing System is a power efficient multi-core microprocessor for use in system-on-chip (SoC) applications. The proAptiv Multiprocessing System combines a deep pipeline with multi-issue out of order execution for improved computational throughput. The proAptiv Multiprocessing System can contain one to six MIPS32r3 proAptiv cores, system level coherence manager with L2 cache, optional coherent I/O port, and optional floating point unit. Signed-off-by:
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Leonid Yegoshin authored
Add processor identifiers for single core and multi-core proAptiv processors. Signed-off-by:
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Leonid Yegoshin authored
For MIPS32R3 supported cores, the EHINV bit needs to be set when invalidating the TLB. This is necessary because the legacy software method of representing an invalid TLB entry using an unmapped address value is not guaranteed to work. Signed-off-by:
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Steven J. Hill authored
MIPS32R3 introduced a new set of Segmentation Control registers which increase the flexibility of the segmented-based memory scheme. Signed-off-by:
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Leonid Yegoshin authored
New Aptiv cores support the TLBINVF instruction for flushing the VTLB. Signed-off-by:
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Markos Chandras authored
The UNIQUE_ENTRYHI definition was duplicated whenever there was the need to flush the TLB entries. We move this common definition to a header file. Signed-off-by:
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Leonid Yegoshin authored
Signed-off-by:
David Daney <david.daney@cavium.com> Signed-off-by:
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Markos Chandras authored
Add support for including VPE and TC ids in /proc/cpuinfo output as appropriate when MT/SMTC is enabled. Reviewed-by:
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Leonid Yegoshin authored
Commit 225ae5fd "MIPS: Malta: Fix interupt number of CBUS UART" fixed the IRQ number for the ttyS2 CBUS UART. However, this now conflicts with the GIC IPI1 interrupt in CMP platforms. The Malta interrupt code arbitrarily binds IPIs to INT2 and INT3 and since ttyS2 uses the INT2 IRQ line, closing the device disables the INT2 interrupt and this effectively disables the IPI1 interrupt as well. This patch is mainly a workaround until the Malta code is fixed properly. Signed-off-by:
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Leonid Yegoshin authored
The cacheer register is always implemented in the same way in the MIPS32r2 Imgtec cores so print the ES bit when an cache error occurs. Signed-off-by:
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Steven J. Hill authored
If GIC is present, then use it to send IPIs between the cores. Using GIC for IPIs is simpler and is usable for multicore systems compared to the existing way of doing IPIs where all VPEs had to be disabled for another VPE to access the Cause register in one of the TCs and enable all the VPEs back. Signed-off-by:
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Markos Chandras authored
According to Documentation/cpu-hotplug.txt, the cpu_present_mask should contain all the CPUs which are present in the system. Therefore, all the TCs currently present in the system should be marked as 'present' even if they will never be brought online. Signed-off-by:
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Markos Chandras authored
According to MIPS32 and MIPS64 PRA documents, a value of 7 in IL and DL fields is marked as "Reserved" so panic if the core uses this value in the config1 register. Also simplify the code a little bit. Signed-off-by:
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Markos Chandras authored
The mips_mt_* symbols are only built and exported if CONFIG_MIPS_MT is enabled. Fixes the following build problem when CONFIG_SMP is enabled but CONFIG_MIPS_MT is not. arch/mips/built-in.o: In function `cmp_prepare_cpus': arch/mips/kernel/smp-cmp.c:197: undefined reference to `mips_mt_set_cpuoptions' Signed-off-by:
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Ilia Mirkin authored
Fix nvram_read_alpha2 copying too many bytes over the ssb_sprom structure. Also fix the arguments of the read_macaddr, although the code was technically not wrong before due to an extra dereference. Signed-off-by:
Ilia Mirkin <imirkin@alum.mit.edu> Acked-by:
Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by:
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Hauke Mehrtens authored
This adds support for vectored interrupt which is supported by the SoC using a MIPS 74K CPU like the BCM4716 and BCM4706. Signed-off-by:
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Hauke Mehrtens authored
The BCM47XX SoC code missed a cpu-feature-overrides.h header file, this patch adds it. This code supports a long line of SoCs with different features so for some features we still have to rely on the runtime detection. This was crated by checking the features of a BCM4712, BCM4704, BCM5354, BCM4716 and BCM4706 SoC and then tested on these SoCs. There are some SoCs missing but I hope they do not have any more or less features. Signed-off-by:
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Hauke Mehrtens authored
Move the possible nvram sizes from the stack into the data segment Signed-off-by:
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Hauke Mehrtens authored
plat_irq_dispatch() is called from asm code, add asmlinkage. Signed-off-by:
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Hauke Mehrtens authored
The defconfig for bcm47xx contained lots of driver which are not special for these SoCs and missed on the other side some some drivers for parts essential for these SoC and only found on here. The flash, usb and some Ethernet driver were missing. Signed-off-by:
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Hauke Mehrtens authored
The BCM47xx SoCs have a 8250 serial compatible console at address 0x18000300 and an other at 0x18000400. On most devices 0x18000300 is wired to some pins on the board, we should use that. This is the smae for the AI (bcma) and the SB (ssb) bus, this is some offset on the chip common core. Signed-off-by:
Aaro Koskinen <aaro.koskinen@iki.fi> Signed-off-by:
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Hauke Mehrtens authored
bcm47xx only uses the CFE code for early print to a console, but that is also possible with a early print serial 8250 driver. The CFE api init causes hangs somewhere in prom_init_cfe() on some devices like the Buffalo WHR-HP-G54 and the Asus WL-520GU. This was reported in https://dev.openwrt.org/ticket/4061 and https://forum.openwrt.org/viewtopic.php?id=17063 This will remove all the CFE handling code from bcm47xx. Signed-off-by:
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Hauke Mehrtens authored
Recently the output of "system type" in /proc/cpuinfo was changed to Broadcom BCM4730 (Some sample board), but it is better to just print the SoC name in the "system type" entry. The board name will be added in the machine entry later. Signed-off-by:
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Jonas Gorski authored
All MIPS cores on BCM63XX identify as Broadcom, not MIPS, so no need to support non-broadcom MIPS CPUs. This also ensures that CPU_BMIPS is always selected. Signed-off-by:
Jonas Gorski <jogo@openwrt.org> Signed-off-by:
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