Merge "mvebu soc for 4.7" from Gregory CLEMENT:

- Clock framework cleanup with the "Remove CLK_IS_ROOT" series

* tag 'mvebu-soc-4.7-1' of git://git.infradead.org/linux-mvebu:
  ARM: dove: Remove CLK_IS_ROOT
  ARM: orion5x: Remove CLK_IS_ROOT
  ARM: mv78xx0: Remove CLK_IS_ROOT

Merge tag 'davinci-for-v4.7/soc-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

Merge "DaVinci SoC updates for v4.7 (part 2)" from Sekhar Nori:

These patches provide ability to add non-PSC
clocks to DaVinci clock framwork and are
required to support USB PHY clock setting from
USB PHY driver.

* tag 'davinci-for-v4.7/soc-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: da850: use clk->set_parent for async3
  ARM: davinci: Move clock init after ioremap.

Merge "NXP LPC32xx mach updates for v4.7" from Vladimir Zapolskiy:

This includes a few nonfunctional clean-ups for NXP LPC32xx:
* removed leftover from restart code migration to a watchdog driver
* removed dead code leftovers from migration to CCF driver
* fix double const qualifier

* tag 'lpc32xx-soc-4.7' of git://github.com/vzapolskiy/linux-lpc32xx:
  ARM: lpc32xx: remove duplicate const on lpc32xx_auxdata_lookup
  ARM: lpc32xx: remove leftovers of legacy clock source and provider drivers
  ARM: lpc32xx: remove reboot header file

The change adds a list of files for maintenance under NXP LPC32xx
section, the listed files are NXP LPC32xx SoC series mach files,
DTS files of NXP LPC32xx SoC powered boards and NXP LPC32xx SoC
peripheral drivers, most of the peripheral driver file names match
'lpc32xx' pattern.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Roland Stigge added initial support of NXP LPC32xx SoC series and
first boards powered by it, but for a while since v3.18-rc1 the
SoC support is unmaintained and became stale.

Vladimir Zapolskiy and Sylvain Lemieux expressed interest in
continuation of NXP LPC32xx maintenance, reflect this in MAINTAINERS
record file for better communication with Linux kernel community.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

A record of NXP LPC32xx SoC support is lost between LMxx hwmon drivers
and lockdep, rename and move it to a place where all other ARM
SoC and machines settle.

Note, NXP LPC32xx maintenance is actually about SoC series itself, SoC
peripherals and a number of machines powered by LPC32xx SoC, so while
we are here correct the title name to emphasize that the maintenance
concerns SoC support in general.
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'omap-for-v4.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Merge "SoC related changes for omaps for v4.7 merge window" from Tony Lindgren:

- Remove now unnecessary multi vs single SoC compile time optimizations
  as we are now using multiarch

- Configure dra7 powerdomains

- Clarify why omap-wakeupgen does not need to handle FROZEN transitions

- Add dra7 module configuration for MaASP, PWMSS and timer 12

- Add RTC module configuration unlock and lock functions

- Fix hwmod idle state sanity check sequence

* tag 'omap-for-v4.7/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: wakeupgen: Add comment for unhandled FROZEN transitions
  ARM: OMAP: DRA7: powerdomain data: Remove wrong OSWR capability
  ARM: OMAP: DRA7: powerdomain data: Fix "ON" state for memories
  ARM: OMAP: DRA7: powerdomain data: Erratum i892 workaround: Disable core INA
  ARM: OMAP2+: remove redundant multiplatform checks
  ARM: OMAP2+: hwmod: fix _idle() hwmod state sanity check sequence
  ARM: DRA7: hwmod: Add data for GPTimer 12
  ARM: AMx3xx: RTC: Add lock and unlock functions
  ARM: DRA7: RTC: Add lock and unlock functions
  ARM: OMAP2+: hwmod: RTC: Add lock and unlock functions
  ARM: OMAP2+: DRA7: Add hwmod entries for PWMSS
  ARM: DRA7: hwmod: Add data for McASP1/2/4/5/6/7/8
  ARM: DRA7: clockdomain: Implement timer workaround for errata i874
  ARM: OMAP2+: hwmod: Fix updating of sysconfig register

Remove redundant duplicate const, which is found by smatch:

  arch/arm/mach-lpc32xx/phy3250.c:162:42: warning: duplicate const
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

After switching the platform to common clock framework there is no
more need to keep dead code in arch/arm/mach-lpc32xx, which glued
legacy clock source and clock provider drivers, remove the leftovers.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

The header file "reboot.h" is no longer needed, following
the migration of the restart code into the pnx4008 watchdog.
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>

This flag is a no-op now (see commit 47b0eeb3 "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.

Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This flag is a no-op now (see commit 47b0eeb3 "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.

Cc: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

This flag is a no-op now (see commit 47b0eeb3 "clk: Deprecate
CLK_IS_ROOT", 2016-02-02) so remove it.

Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>

The da850 family of processors has an async3 clock domain that can be
muxed to either pll0_sysclk2 or pll1_sysclk2. Now that the davinci clocks
have a set_parent callback, we can use this to control the async3 mux
instead of a stand-alone function.

This adds a new async3_clk and sets the appropriate child clocks. The
default is use to pll1_sysclk2 since it is not affected by processor
frequency scaling.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: drop unnecessary comment]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Some clocks (such as the USB PHY clocks in DA8xx) will need to use iomem.
The davinci_common_init() function must be called before the ioremap, so
the clock init is now split out as separate function.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Merge "ARM: Add OXNAS Platform Support" from Neil Armstrong

This is for the ARM926 based ox810 chip used in some older
NAS appliances. There is another related ox820 chip based on
ARM11 that might get added here later.

* tag 'ox810se-arm-v4.6-rc3' of https://github.com/superna9999/linux:
  MAINTAINERS: add maintainer entry for ARM/OXNAS platform
  ARM: Add new mach-oxnas
  irqchip: versatile-fpga: add new compatible for OX810SE SoC

This patch update ARM Versatile Express entry to cover bits needed for
Cortex-M Prototyping System (MPS2 platform). So patches for the latter
are collected by existing Vexpress and Juno maintainers (Liviu, Sudeep,
Lorenzo) and find their way upstream via Vexpess and/or Juno trees.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

The Cortex-M Prototyping System (or V2M-MPS2) is designed for
prototyping and evaluation Cortex-M family of processors including the
latest Cortex-M7

It comes with a range of useful peripherals including 8MB single cycle
SRAM, 16MB PSRAM, Ethernet, QSVGA touch screen panel, 4bit RGB VGA
connector, Audio, SPI and GPIO.
Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

Add a maintainer entry for ARM/OXNAS platform and add myself as a maintainer.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Add mach-oxnas directory containing Kconfig.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Under the OX810SE, this exact same interface is used as "Reference Peripheral
Specification" Interrupt Controller, so add a new compatible string in order
to support the Oxford Semiconductor OX810SE SoC interrupt controller.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>

Put nodes after of_address_to_resource() in case the nodes might be
released while parsing in them.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

Merge tag 'renesas-soc-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Renesas ARM Based SoC Updates for v4.7" from Simon Horman:

Drop support for Cortex A8 in timer code

* tag 'renesas-soc-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: timer: Drop support for Cortex A8
  ARM: shmobile: timer: Fix preset_lpj leading to too short delays
  Revert "ARM: dts: porter: Enable SCIF_CLK frequency and pins"
  ARM: dts: r8a7791: Don't disable referenced optional clocks

Merge tag 'davinci-for-v4.7/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci into next/soc

Merge "DaVinci SoC updates for v4.7" from Sekhar Nori:

These are preparatory patches to support a USB PHY driver for USB on DA850
SoC. This should eventually lead to USB working again on this device.

* tag 'davinci-for-v4.7/soc' of git://git.kernel.org/pub/scm/linux/kernel/git/nsekhar/linux-davinci:
  ARM: davinci: clk: add set_parent callback for mux clocks
  ARM: davinci: da8xx: move usb code to new file
  ARM: davinci: use IRQCHIP_DECLARE for cp_intc
  ARM: davinci: remove unused DA8XX_NUM_UARTS
  ARM: davinci: simplify call to of populate
  ARM: DaVinci USB: removed deprecated properties from MUSB config

Merge tag 'for-v4.7/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.7/soc

ARM: OMAP2+: first set of hwmod changes for v4.7

For the DRA7xx platform, add IP block data for the McASP, PWMSS,
and GPTimer12 IP blocks.  Add lock and unlock functions for the
RTC IP blocks on the DRA7xx, AM33xx, and AM43xx devices.  And add
a fix for the hwmod core for device driver unbind operations for
IP blocks with hardreset lines.

Basic build, boot, and PM test results are available here:

http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.7/20160410132119/

Note that the testbed here does not have the DRA7xx board included yet.

Commit edf41009 ("ARM: shmobile: sh7372 dtsi: Remove Legacy
file") removed the DTS for the last shmobile SoC with a Cortex A8 CPU
core (sh7372 aka SH-Mobile AP4), hence drop support for it in the
loops-per-jiffy preset code.

As "div" is always 1 for supported contemporary ARM processors, we can
simplify the code:
  - Absorb shmobile_setup_delay_hz(), which was always called with
    mult = div = 1,
  - Return earlier if the Cortex A7/A15 arch timer exists and support is
    enabled.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

On all shmobile ARM SoCs, loop-based delays may complete early, which
can be after only 1/3 (Cortex A9) or 1/2 (Cortex A7 or A15) of the
minimum required time.

This is caused by calculating preset_lpj based on incorrect assumptions
about the number of clock cycles per loop:
  - All of Cortex A7, A9, and A15 run __loop_delay() at 1 loop per
    CPU clock cycle,
  - As of commit 11d4bb1b ("ARM: 7907/1: lib: delay-loop: Add
    align directive to fix BogoMIPS calculation"), Cortex A8 runs
    __loop_delay() at 1 loop per 2 instead of 3 CPU clock cycles.

On SoCs with Cortex A7 and/or A15 CPU cores, this went unnoticed, as
delays use the ARM arch timer if available. R-Car Gen2 doesn't work if
the arch timer is disabled. However, APE6 can be used without the arch
timer.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

This reverts commit 19417bd9 ("ARM: dts: porter: Enable SCIF_CLK
frequency and pins") as according to
http://elinux.org/File:R-CarM2-KOELSCH_PORTER-B_PORTER_C_Comparison.pdf
the external oscillator for SCIF_CLK is not mounted on the porter boards.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

clk_get on a disabled clock node will return EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their clocks property.

Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them to prevent this.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

Introduce a set_parent callback that will be used for mux clocks, such as
the USB PHY muxes and the async3 clock domain mux.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: checkpatch fixes]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

We will be adding more da8xx-specific code for phy and clocks, so it will
be better to have this in a separate file. This way we don't have a bunch
of #ifdefs for all of the da8xx stuff.

While at it, fix some checkpatch warnings coming from existing code.
Signed-off-by: David Lechner <david@lechnology.com>
[nsekhar@ti.com: typo and checkpatch fixes]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Remove boilerplate code by using IRQCHIP_DECLARE macro.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

DA8X_NUM_UARTS not used in the code anywhere and should be determined
by DT anyway.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Take advantage of of_platoform_default_populate convience function.
Signed-off-by: David Lechner <david@lechnology.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

The following properties of the musb_hdrc_config structure
are deprecated and no longer required/used by the MUSB driver:

.dyn_fifo
.soft_con
.dma
.dma_channels
.eps_bits
Signed-off-by: Petr Kulhavy <petr@barix.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>

Merge tag 'sti-soc-for-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti into next/soc

Highlights:
-----------
 - Add CPUFreq and RProc drivers to STI maintainers file list
 - Improve STi's menuconfig help entry

* tag 'sti-soc-for-v4.7-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mcoquelin/sti:
  ARM: STi: Update platform level menuconfig 'help'
  MAINTAINERS: Add ST's Remote Processor Driver to ARM/STI ARCHITECTURE
  MAINTAINERS: Add ST's CPUFreq driver to the STI file list
Signed-off-by: Olof Johansson <olof@lixom.net>

FROZEN hotplug notifiers are not handled and do not have to be. Insert
a comment to remember that the lack of the FROZEN transitions is no
accident.

Cc: Tony Lindgren <tony@atomide.com>
Cc: Santosh Shilimkar <ssantosh@kernel.org>
Cc: linux-omap@vger.kernel.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Acked-by: Santosh Shilimkar <ssantosh@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Open Switch Retention(OSWR) is a retention state which is unsupported
in DRA7 SoC. This state is achieved when power state is set to
retention and logic power state is set to OFF.

Even though DRA7 architecture is a OMAP derivative, none of the
powerdomains are actually implemented to achieve OSWR in the SoC.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

When the power domain is in "ON" state, the memories should be always
in "ON", even though the hardware register allows other states to be
written, wrong states may confuse certain hardware blocks.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

Erratum i892 as will be documented in the upcoming G or later revision
of DRA7xx/ AM57xx errata documentation (SPRZ398F) states that L3 clock
needs to be kept active all the time to ensure that asymmetric aging
degradation is minimal and within the design allowed margin.

By allowing core domain to transition to INA and allowing L3 clock to be
turned off for extended periods of time, there is a risk of functional
issues and device failure as a result.

Ref: http://www.ti.com/lit/er/sprz429h/sprz429h.pdfSigned-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>