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  1. 07 Mar, 2014 4 commits
    • Imre Deak's avatar
      drm/i915: power domains: add vlv power wells · 77961eb9
      Imre Deak authored
      Based on an early draft from Jesse.
      
      Add support for powering on/off the dynamic power wells on VLV by
      registering its display and dpio dynamic power wells with the power
      domain framework.
      
      For now power on all PHY TX lanes regardless of the actual lane
      configuration. Later this can be optimized when the PHY side setup
      enables only the required lanes. Atm, it enables all lanes in all
      cases.
      
      v2:
      - undef function local COND macro after its last use (Ville)
      - Take dev_priv->irq_lock around the whole sequence of
        intel_set_cpu_fifo_underrun_reporting_nolock() and
        valleyview_disable_display_irqs(). They are short and releasing
        the lock in between only makes proving correctness more difficult.
      - sanitize local var names in vlv_power_well_enabled()
      v3:
      - rebase on latest -nightly
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      [danvet: Resolve conflict due to my changes in the previous patch.
      Also throw in an assert_spin_locked for safety. And finally appease
      checkpatch.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      77961eb9
    • Imre Deak's avatar
      drm/i915: check pipe power domain when reading its hw state · b5482bd0
      Imre Deak authored
      We can read out the pipe HW state only if the required power domain is
      on. If not we consider the pipe to be off.
      
      v2:
      - no change
      v3:
      - push down the power domain checks into the specific crtc
        get_pipe_config handlers (Daniel)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      [danvet: Appease checkpatch.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b5482bd0
    • Imre Deak's avatar
      drm/i915: add port power domains · 319be8ae
      Imre Deak authored
      Parts that poke port specific HW blocks like the encoder HW state
      readout or connector hotplug detect code need a way to check whether
      required power domains are on or enable/disable these. For this purpose
      add a set of power domains that refer to the port HW blocks. Get the
      proper port power domains during modeset.
      
      For now when requesting the power domain for a DDI port get it for a 4
      lane configuration. This can be optimized later to request only the 2
      lane power domain, when proper support is added on the VLV PHY side for
      this. Atm, the PHY setup code assumes a 4 lane config in all cases.
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      319be8ae
    • Imre Deak's avatar
      drm/i915: move modeset_update_power_wells earlier · 77d22dca
      Imre Deak authored
      These functions will be needed by the valleyview specific power well
      update functionality added in an upcoming patch, so move them earlier.
      
      No functional change.
      
      v2:
      - no change
      v3:
      - rebase on latest -nightly
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> (v2)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      77d22dca
  2. 05 Mar, 2014 11 commits
  3. 04 Mar, 2014 1 commit
  4. 02 Mar, 2014 1 commit
    • Daniel Vetter's avatar
      drm/i915: sprinkle static · b5ea642a
      Daniel Vetter authored
      Apparently we've missed a few more than what Fengguang's 0-day tester
      recently reported in i915_irq.c ... Makes sparse happy again (ignore
      some spurious stuff about ksyms of exported functions).
      
      Cc: kbuild test robot <fengguang.wu@intel.com>
      Cc: Imre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      b5ea642a
  5. 14 Feb, 2014 3 commits
  6. 12 Feb, 2014 20 commits