1. 20 May, 2013 16 commits
  2. 17 May, 2013 5 commits
  3. 13 May, 2013 8 commits
  4. 10 May, 2013 7 commits
  5. 07 May, 2013 2 commits
    • Jani Nikula's avatar
      drm/i915: clear the stolen fb before resuming · 1ffc5289
      Jani Nikula authored
      Similar to
      commit 88afe715
      Author: Chris Wilson <chris@chris-wilson.co.uk>
      Date:   Sun Dec 16 12:15:41 2012 +0000
      
          drm/i915: Clear the stolen fb before enabling
      
      but on the resume path.
      
      Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=57191Reported-and-tested-by: default avatarNikolay Amiantov <nikoamia@gmail.com>
      Signed-off-by: default avatarJani Nikula <jani.nikula@intel.com>
      Reviewed-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
      Cc: stable@vger.kernel.org (3.9 only)
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      1ffc5289
    • Ben Widawsky's avatar
      Revert "drm/i915: Calculate correct stolen size for GEN7+" · c4ae25ec
      Ben Widawsky authored
      This reverts commit 03752f5b.
      
      This revert requires a bit of explanation on how I understand things
      work. Internally the architects/designers decide how the stolen encoding
      works. We put it in a doc. BIOS writers take these docs and implement
      it. Driver writers read the doc too, and read the value left by the BIOS
      writers, and then we make magic.
      
      The failing here is that in the docs we had[1] contained two different
      definitions for this register for Gen7. (We have both a PCI register,
      and an MMIO, and each of these were different). At the time [2] of
      03752f5b, we asked the architects what the correct value should be; but
      that doesn't match the reality (BIOS) unfortunately.
      
      So on all machines I can get my hands on, this revert is the right thing
      to do. I've also worked with the product group to confirm that they
      agree this revert is what we should do. People using HW made my "people"
      who both write their own BIOS, and have access to our docs (Apple?).
      Investigations are still ongoing about whether we need to add a list
      of machines needing special handling, but this patch should be the
      right thing for pretty much everyone.
      
      [1] The docs are still wrong on this one. Now instead of two registers with
      two definitions, we have one register with BOTH definitions, progress?
      [2] The open source PRMs have the "wrong" definitions in chapter Volume
      1 part6, section 1.1.12.
      
      This digging was inspired by Paulo.
      
      Cc: Paulo Zanoni <przanoni@gmail.com>
      Signed-off-by: default avatarBen Widawsky <ben@bwidawsk.net>
      Acked-by: default avatarJesse Barnes <jbarnes@virtuousgeek.org>
      [danvet: Augment the patch saying that it's still a bit unclear
      whether there are any machines out there with "wrong" firmware and
      whether we need to add a list to handle them specially.]
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      c4ae25ec
  6. 04 May, 2013 2 commits
    • Imre Deak's avatar
      drm/i915: hsw: fix link training for eDP on port-A · 3ab9c637
      Imre Deak authored
      According to BSpec the link training sequence for eDP on HSW port-A
      should be as follows:
      
      1. link training: clock recovery
      2. link training: equalization
      3. link training: set idle transmission mode
      4. display pipe enable
      5. link training: disable (set normal mode)
      
      Contrary to this at the moment we don't do step 3. and we do step 5.
      before step 4. Fix this by setting idle transmission mode for eDP at
      the end of intel_dp_complete_link_train and adding a new
      intel_dp_stop_link_training function to disable link training. With
      these changes we'll end up with the following functions corresponding
      to the above steps:
      
      intel_dp_start_link_train    -> step 1.
      intel_dp_complete_link_train -> step 2., step 3.
      intel_dp_stop_link_train     -> step 5.
      
      For port-A we'll call intel_dp_stop_link_train only after enabling the
      pipe, for everything else we'll call it right after
      intel_dp_complete_link_train to preserve the current behavior.
      
      Tested on HSW/HSW-ULT.
      
      In v2:
      - Due to a HW issue we must set idle transmission mode for port-A too
        before enabling the pipe. Thanks for Arthur Runyan for explaining
        this.
      - Update the patch subject to make it clear that it's an eDP fix, DP is
        not affected.
      
      v3:
      - rename intel_dp_link_train() to intel_dp_set_link_train(), use 'val'
        instead 'l' as var name. (Paulo)
      Signed-off-by: default avatarImre Deak <imre.deak@intel.com>
      Reviewed-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Tested-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      3ab9c637
    • Daniel Vetter's avatar
      Revert "drm/i915: revert eDP bpp clamping code changes" · 657445fe
      Daniel Vetter authored
      This reverts commit 57c21963.
      
      It's an ugly hack for a Haswell SDV platform where the vbt doesn't
      seem to fully agree with the panel. Since it seems to cause issues on
      real eDP platform let's just kill this hack again.
      Reported-and-tested-by: default avatarJosh Boyer <jwboyer@gmail.com>
      References: https://lkml.org/lkml/2013/5/3/467
      Cc: Paulo Zanoni <przanoni@gmail.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      657445fe