- 09 Mar, 2020 6 commits
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Nikola Cornij authored
[why] Link or DIG BE can't be exposed to a higher stream bandwidth than they can handle. When DSC is required to fit the stream into the link bandwidth, DSC has to be programmed during timing programming to ensure this. Without it, intermittent issues such as black screen after S3 or a hot-plug can be seen. [how] Move DSC programming from enabling stream on link to timing setup. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Yongqiang Sun authored
[Why] System isn't able to enter S0i3 due to not send display count 0 to smu. When dpms off, clk changed flag is cleared alreay, and it is checked when doing optimized bandwidth, and update clocks is bypassed due to the flag is unset. [How] Remove check flag incide the function since watermark values and clocks values are checked during update to determine whether to perform it, no need to check it again outside the function. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Braden Bakker authored
[What] Need debug options to control lightl/deep sleep [How] Add registry for memory power control Signed-off-by:
Braden Bakker <Braden.Bakker@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Wenjing Liu authored
[why] It is possible even if sink signal is MST but driver enables SST stream. We should not determine if we should do MST authentication based on sink's capability. Instead we should determine whether to do MST authentication based on what we have enabled in stream. Signed-off-by:
Wenjing Liu <Wenjing.Liu@amd.com> Reviewed-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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Isabel Zhang authored
[Why] So the values of stay count and bstatus can be easily viewed during debugging. [How] Add stay count and bstatus values to be outputted in HDCP log Signed-off-by:
Isabel Zhang <isabel.zhang@amd.com> Reviewed-by:
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Martin Leung authored
[why] nv14 previously inherited soc bb from generic dcn 2, did not match watermark values according to memory team [how] add nv14 specific soc bb: copy nv2 generic that it was using from before, but changed num channels to 8 Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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- 06 Mar, 2020 18 commits
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Felix Kuehling authored
Otherwise BOs may wait for the fence indefinitely and never be destroyed. v2: Signal the fence right after destroying queues to avoid unnecessary delaye-delete in kfd_process_wq_release Signed-off-by:Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by:
xinhui pan <xinhui.pan@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Monk Liu authored
and disable MC resum in VCN2.0 as well those are not concerned by VF driver Singed-off-by:
darlington Opara <darlington.opara@amd.com> Signed-off-by:
Jinage Zhao <jiange.zhao@amd.com> Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Acked-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Monk Liu authored
support IB test on dec/enc ring disable ring test on dec/enc ring (MMSCH limitation) v2: squash in unused variable warning fix Singed-off-by:
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Monk Liu authored
something need to do for VCN2.0 enablement on SRIOV: 1)use one dec ring and one enc ring 2)allocate MM table for MMSCH usage 3)implement SRIOV version vcn_start which orgnize vcn programing with patcket format and implement start mmsch for to run those packet 4)doorbell is changed for SRIOV Singed-off-by:
Emily Deng <Emily.Deng@amd.com> Signed-off-by:
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Monk Liu authored
MMSCH doesn't support jpeg ring on SRIOV Signed-off-by:
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Monk Liu authored
Signed-off-by:
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Yong Zhao authored
Because too many things are involved in this workaround, we need more comments to avoid pitfalls. Signed-off-by:
Yong Zhao <Yong.Zhao@amd.com> Acked-by:
Philip Yang <philip.yang@amd.com> Signed-off-by:
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Yong Zhao authored
Add "CP" to AMDGPU_GEM_CREATE_MQD_GFX9 to indicate it is only for CP MQD buffer. Signed-off-by:
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Andrey Grodzovsky authored
Problem: During GU reset PSP's sysfs was being wrongly reinitilized during call to amdgpu_device_ip_late_init which was failing with duplicate error. Fix: Move psp_sysfs_init to psp_sw_init to avoid this. Add guards in sysfs file's read and write hook agains premature call if PSP is not finished initialization. Signed-off-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by:
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Jacob He authored
SPM access the video memory according to SPM_VMID. It should be updated with the job's vmid right before the job is scheduled. SPM_VMID is a global resource Signed-off-by:
Jacob He <jacob.he@amd.com> Reviewed-by:
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John Clements authored
check UMC status and exit prior to making and erroneus register access this resolved unexpected behaviour with UMC indexing mode broadcasting writes Reviewed-by:
Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by:
John Clements <john.clements@amd.com> Signed-off-by:
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Guchun Chen authored
On arcturus, DF-Cstate needs to be toggled off/on before and after accessing UMC error counter and error address registers, otherwise, clearing such registers may fail. Signed-off-by:
Guchun Chen <guchun.chen@amd.com> Reviewed-by:
Tao Zhou <tao.zhou1@amd.com> Signed-off-by:
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John Clements authored
mitigates race condition on BACO reset between GPU bootcode and driver reload Reviewed-by:
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Hawking Zhang authored
add arcturus xgmi/wafl pcs err status group to support PCS error detection and report on arcturus Signed-off-by:
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Hawking Zhang authored
Now driver will report XGMI/WAFL PCS error through sysfs xgmi_wafl_err_count node on Vega20 Signed-off-by:
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Hawking Zhang authored
Since from vega20, hardware supports run-time detect and report XGMI/WAFL PCS ras error. Add helper functions to walkthrough every type of ras error and report it if any. Signed-off-by:
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Hawking Zhang authored
add wafl2 smn address and shift mask definition header files Signed-off-by:
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Hawking Zhang authored
add xgmi ip smn address and shift mask header files Signed-off-by:
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- 05 Mar, 2020 16 commits
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Nathan Chancellor authored
Clang warns: drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.c:147:31: warning: address of 'pipe_ctx->plane_res' will always evaluate to 'true' [-Wpointer-bool-conversion] if (!pipe_ctx || !&pipe_ctx->plane_res || !&pipe_ctx->stream_res) ~ ~~~~~~~~~~^~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.c:147:56: warning: address of 'pipe_ctx->stream_res' will always evaluate to 'true' [-Wpointer-bool-conversion] if (!pipe_ctx || !&pipe_ctx->plane_res || !&pipe_ctx->stream_res) ~ ~~~~~~~~~~^~~~~~~~~~ 2 warnings generated. As long as pipe_ctx is not NULL, the address of members in this struct cannot be NULL, which means these checks will always evaluate to false. Fixes: 4c1a1335 ("drm/amd/display: Driverside changes to support PSR in DMCUB") Link: https://github.com/ClangBuiltLinux/linux/issues/915Reviewed-by:Nick Desaulniers <ndesaulniers@google.com> Signed-off-by:
Nathan Chancellor <natechancellor@gmail.com> Signed-off-by:
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Hersen Wu authored
This interface is for dGPU Navi1x. Linux dc-pplib interface depends on window driver dc implementation. For Navi1x, clock settings of dcn watermarks are fixed. the settings should be passed to smu during boot up and resume from s3. boot up: dc calculate dcn watermark clock settings within dc_create, dcn20_resource_construct, then call pplib functions below to pass the settings to smu: smu_set_watermarks_for_clock_ranges smu_set_watermarks_table navi10_set_watermarks_table smu_write_watermarks_table For Renoir, clock settings of dcn watermark are also fixed values. dc has implemented different flow for window driver: dc_hardware_init / dc_set_power_state dcn10_init_hw notify_wm_ranges set_wm_ranges For Linux smu_set_watermarks_for_clock_ranges renoir_set_watermarks_table smu_write_watermarks_table dc_hardware_init -> amdgpu_dm_init dc_set_power_state --> dm_resume therefore, linux dc-pplib interface of navi10/12/14 is different from that of Renoir. v2: add missing unlock in error case Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
To avoid compile errors on other platforms. Signed-off-by:
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Andrey Grodzovsky authored
Starts USBC PD FW download and reads back the latest FW version. v2: Move sysfs file creation to late init Add locking around PSP calls to avoid concurrent access to PSP's C2P registers Signed-off-by:
Luben Tuikov <luben.tuikov@amd.com> Signed-off-by:
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Andrey Grodzovsky authored
Add the programming sequence. v2: Change donwload wait loop to more efficient. Move C2PMSG_CMD_GFX_USB_PD_FW_VER defintion v3: Fix lack of loop counter increment typo v4: Remove superflous status reg read Signed-off-by:
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Andrey Grodzovsky authored
Used to load power Delivery FW to PSP. Signed-off-by:
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Hawking Zhang authored
The ROMC_INDEX/DATA offset was changed to e4/e5 since from smuio_v11 (vega20/arcturus). Signed-off-by:
Candice Li <Candice.Li@amd.com> Reviewed-by:
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Hawking Zhang authored
HDP ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by:
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Hawking Zhang authored
GFX ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by:
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Hawking Zhang authored
MMHUB ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by:
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Hawking Zhang authored
SDMA ras error counters are dirty ones after cold reboot Read operation is needed to reset them to 0 Signed-off-by:
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jianzh authored
Navi12 VK CTS subtest timestamp.calibrated.dev_domain_test failed because mmRLC_CAPTURE_GPU_CLOCK_COUNT register cannot be written in VF due to security policy. Solution: use a VF-accessible timestamp register pair mmGOLDEN_TSC_COUNT_LOWER/UPPER for SRIOV case. v2: according to Deucher Alexander's advice, switch to mmGOLDEN_TSC_COUNT_LOWER/UPPER for both bare metal and SRIOV. Signed-off-by:
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Prike Liang authored
When hit COMBINATIONAL_BYPASS the mclk will be bypass and can export fclk frequency to user usage. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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Prike Liang authored
This fix will handle some MP1 FW issue like as mclk dpm table in renoir has a reverse dpm clock layout and a zero frequency dpm level as following case. cat pp_dpm_mclk 0: 1200Mhz 1: 1200Mhz 2: 800Mhz 3: 0Mhz Signed-off-by:
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Tiecheng Zhou authored
With new L1 policy, some regs are blocked at guest and they are programed at host side. So skip programing the regs under sriov. the regs are: GCMC_VM_FB_LOCATION_TOP GCMC_VM_FB_LOCATION_BASE MMMC_VM_FB_LOCATION_TOP MMMC_VM_FB_LOCATION_BASE GCMC_VM_SYSTEM_APERTURE_HIGH_ADDR GCMC_VM_SYSTEM_APERTURE_LOW_ADDR MMMC_VM_SYSTEM_APERTURE_HIGH_ADDR MMMC_VM_SYSTEM_APERTURE_LOW_ADDR HDP_NONSURFACE_BASE HDP_NONSURFACE_BASE_HI GCMC_VM_AGP_TOP GCMC_VM_AGP_BOT GCMC_VM_AGP_BASE Acked-by:
Tiecheng Zhou <Tiecheng.Zhou@amd.com> Signed-off-by:
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abdoulaye berthe authored
[Why] Some lttpr devices do not work properly when lttpr mode is configured after link settings. [How] Move lttpr configuration before lane settings. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
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