- 02 Jun, 2014 7 commits
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Rafał Miłecki authored
Thanks to advanced RE of fglrx we finally know what exactly needs to be handled of AFMT change. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Rafał Miłecki authored
Recent RE efforts revealed ops performed by fglrx during HDMI setup. This mostly adds masks to r/w ops plus few single missing bits. This has been tested for possible regressions on: 1) DCE2 HD2400 (RV610) 2) DCE3 HD3470 (RV620) For a reference and details see: https://bugzilla.kernel.org/show_bug.cgi?id=76231Signed-off-by:
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Rafał Miłecki authored
What initially seemed to be a typo in fglrx (using register 0x740c instead of 0x74dc) appeared to be a correct behavior. DCE3 has ACR and CRC registers swapped which explains why we needed WREG32(HDMI0_AUDIO_CRC_CONTROL + offset, 0x1000); This has been tested for possible regressions on DCE3 HD3470 (RV620). Signed-off-by:
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Rafał Miłecki authored
DCE 3.1 and 3.2 should be programmed in a different way than DCE 2 and DCE 3. The order of setting registers and sets of registers are different. It's still unsure how we will handle DCE 3.1 vs. DCE 3.2, since they have few differences as well. For now separate DCE 2 and DCE 3 path, so we can work on it without a risk of breaking DCE 3.1+. This has been tested for possible regressions on DCE32 HD4550 (RV710). Signed-off-by:
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Christian König authored
This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Christian König authored
This patch implements support for VRAM page table entry compression. PTE construction is enhanced to identify physically contiguous page ranges and mark them in the PTE fragment field. L1/L2 TLB support is enabled for 64KB (SI/CIK) and 256KB (NI) PTE fragments, significantly improving TLB utilization for VRAM allocations. Linear store bandwidth is improved from 60GB/s to 125GB/s on Pitcairn. Unigine Heaven 3.0 sees an average improvement from 24.7 to 27.7 FPS on default settings at 1920x1200 resolution with vsync disabled. See main comment in radeon_vm.c for a technical description. v2 (chk): rebased and simplified. v3 (chk): add missing hw setup v4 (chk): rebased on current drm-fixes-3.15 v5 (chk): fix comments and commit text Signed-off-by:
Jay Cornwall <jay@jcornwall.me> Signed-off-by:
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Alex Deucher authored
The i2c and aux buses use the same pads so add a mutex to protect access to the pads. Signed-off-by:
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- 30 May, 2014 3 commits
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Dave Airlie authored
This adds an encoder type for DP MST encoders. Reviewed-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Jani Nikula authored
This makes drm_get_encoder_name() thread safe. Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01\ .ptsecurity.ru Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
David Herrmann <dh.herrmann@gmail.com> Signed-off-by:
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Jani Nikula authored
This makes drm_get_connector_name() thread safe. [airlied: fix to build.] Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01.ptsecurity.ruSigned-off-by:
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- 27 May, 2014 8 commits
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Thierry Reding authored
Commit 9dc40560 (drm/dp: let drivers specify the name of the I2C- over-AUX adapter) introduced a new field but didn't add the proper kernel-doc for it. Signed-off-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
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David Herrmann authored
shmem_read_mapping_page() uses mapping_gfp_mask(mapping) as default gfp mask. No reason to use shmem_read_mapping_page_gfp() directly if we want the default behavior. Acked-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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David Herrmann authored
shmem supports page-relocations during swapin since quite some time. It was implemented in: commit bde05d1c Author: Hugh Dickins <hughd@google.com> Date: Tue May 29 15:06:38 2012 -0700 shmem: replace page if mapping excludes its zone The gem-comment about wrongly placed DMA32 pages is no longer valid. Replace it with a proper comment but keep the BUG_ON() to verify correct shmem behavior. Signed-off-by:Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Benoit Taine authored
This issue was reported by coccicheck using the semantic patch at scripts/coccinelle/api/memdup.cocci Signed-off-by:
Benoit Taine <benoit.taine@lip6.fr> Signed-off-by:
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Jean Delvare authored
The shmobile DRM driver is only useful on SuperH and shmobile unless build testing. I am dropping the SuperH dependencies though because the driver doesn't even build there, so in practice it is an arm-only driver for now. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Acked-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Jean Delvare authored
The Renesas R-Car Display Unit driver is only useful on shmobile unless build testing. The LVDS output is useful on an even more reduced hardware set. Signed-off-by:
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Daniel Vetter authored
DRM is pretty much the main user of this stuff (if we ignore the sysfs interface used by X, i.e. by the same gang of people writing the drm drivers). So shovel it into Dave's responsibility to avoid patches getting lost on lkml. With this get_maintainers will rout vgaarb and switcheroo patches correctly. Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Dave Airlie <airlied@redhat.com> Cc: linux-kernel@vger.kernel.org References: https://lkml.org/lkml/2014/5/25/94Signed-off-by:
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Sagar Kamble authored
Started documenting drm properties for drm drivers. This patch provides information about properties in drm, i915, psb and cdv/gma-500. Information about other properties can be added on top of these. v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau, omap, qxl, radeon, rcar-du v3: Removed "Property Object" column since it is implementation related. Property type column refined.[Ville's review comments] v4: Removed whitespace warnings and minor nits. [Randy's review comments] v5: Restructured output for ENUM properties v6: Review comments on formatting the table. [Laurent's review comments] v7: Minor restructuring. [Laurent's review comments] Cc: Rob Landley <rob@landley.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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- 26 May, 2014 4 commits
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Alexandre Courbot authored
The kerneldoc header of ttm_bo_create() was referring to another (nonexisting) function and had a few obsolete or incorrect arguments. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Reviewed-by:
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Daniel Thompson authored
The 800x600 (SVGA) screen resolution was lacking in the set of built-in selectable EDID screen resolutions that can be used to repair misbehaving monitor firmware. This patch adds the related data set and expands the documentation. Note that the SVGA bit occupies a different byte to all the existing users of the established timing bits forcing a rework of the ESTABLISHED_TIMINGS_BITS macro. Tested new EDID on an aged (and misbehaving) industrial LCD panel; existing EDIDs still pass edid-decode's checksum checks. Signed-off-by:
Daniel Thompson <daniel.thompson@linaro.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: David Airlie <airlied@linux.ie> Cc: Carsten Emde <C.Emde@osadl.org> Cc: linux-doc@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
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Masanari Iida authored
Fix spelling typo in DocBook/drm.tmpl Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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- 23 May, 2014 1 commit
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Dave Airlie authored
This just adds the defines from the DP 1.2 spec, which we will use later. fix some DP MST to 1.2 MST Signed-off-by:
Jingoo Han <jg1.han@samsung.com>
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- 19 May, 2014 6 commits
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ssh://people.freedesktop.org/~/linuxDave Airlie authored
Pull in latest updates to AST driver. * 'ast-updates' of ssh://people.freedesktop.org/~/linux: drm/ast: initial DP501 support (v0.2) drm/ast: rename the mindwm/moutdwm and deinline them drm/ast: resync the dram post code with upstream drm/ast: add AST 2400 support. drm/ast: add widescreen + rb modes from X.org driver (v2)
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Dave Airlie authored
This is the initial attempt at porting the DP501 code from the userspace driver, the firmware file is in http://people.freedesktop.org/~airlied/ast_dp501_fw.bin this should really be exposed as another encoder/connector that is cloneable v0.2: init 3rd tx properly, add scratch reduction of VRAM size backup firmware properly. Signed-off-by:
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Dave Airlie authored
we'll need these elsewhere for dp501. Signed-off-by: -
Dave Airlie authored
This resyncs the dram post code with the upstream X.org driver where ast have improved the code for setting up the dram chips. Signed-off-by: -
Dave Airlie authored
This is ported from the userspace driver. Untested on any ast2400 hw so far. Signed-off-by: -
Dave Airlie authored
This syncs up the mode code from the X.org driver upstream, and adds the mode validation step for hw that doesn't have widescreen. v2: (from Egbert Eich <eich@suse.de) squash drm/ast: Use correct structure member for mode validation to avoid bisect regression. In struct drm_display_mode crtc_hdisplay and crtc_vdisplay are holding the crtc parameters after mode fixup. For validation we need hdisplay and vdisplay. Signed-off-by:
Egbert Eich <eich@suse.de> Signed-off-by:
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- 18 May, 2014 1 commit
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- ring init improvements (Chris) - vebox2 support (Zhao Yakui) - more prep work for runtime pm on Baytrail (Imre) - eDram support for BDW (Ben) - prep work for userptr support (Chris) - first parts of the encoder->mode_set callback removal (Daniel) - 64b reloc fixes (Ben) - first part of atomic plane updates (Ville) * tag 'drm-intel-next-2014-05-06' of git://anongit.freedesktop.org/drm-intel: (75 commits) drm/i915: Remove useless checks from primary enable/disable drm/i915: Merge LP1+ watermarks in safer way drm/i915: Make sure computed watermarks never overflow the registers drm/i915: Add pipe update trace points drm/i915: Perform primary enable/disable atomically with sprite updates drm/i915: Make sprite updates atomic drm/i915: Support 64b relocations drm/i915: Support 64b execbuf drm/i915/sdvo: Remove ->mode_set callback drm/i915/crt: Remove ->mode_set callback drm/i915/tv: Remove ->mode_set callback drm/i915/tv: Rip out pipe-disabling nonsense from ->mode_set drm/i915/tv: De-magic device check drm/i915/tv: extract set_color_conversion drm/i915/tv: extract set_tv_mode_timings drm/i915/dvo: Remove ->mode_set callback drm/i915: Make encoder->mode_set callbacks optional drm/i915: Make primary_enabled match the actual hardware state drm/i915: Move ring_begin to signal() drm/i915: Virtualize the ringbuffer signal func ...
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- 16 May, 2014 2 commits
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
Update pull request with drm core patches. Mostly some polish for the primary plane stuff and a pile of patches all over from Thierry. Has survived a few days in drm-intel-nightly without causing ill. I've frobbed my scripts a bit to also tag my topic branches so that you have something stable to pull - I've accidentally pushed a bunch more patches onto this branch before you've taken the old pull request. * tag 'topic/core-stuff-2014-05-05' of git://anongit.freedesktop.org/drm-intel: drm: Make drm_crtc_helper_disable() return void drm: Fix indentation of closing brace drm/dp: Fix typo in comment drm: Fixup flip-work kerneldoc drm/fb: Fix typos drm/edid: Cleanup kerneldoc drm/edid: Drop revision argument for drm_mode_std() drm: Try to acquire modeset lock on panic or sysrq drm: remove unused argument from drm_open_helper drm: Handle ->disable_plane failures correctly drm: Simplify fb refcounting rules around ->update_plane drm/crtc-helper: gc usless connector loop in disable_unused_functions drm/plane_helper: don't disable plane in destroy function drm/plane-helper: Fix primary plane scaling check drm: make mode_valid callback optional drm/edid: Fill PAR in AVI infoframe based on CEA mode list
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Dave Airlie authored
This mode group id_list was never being freed. v2: take David's suggestion to free in minor_free. Signed-off-by:
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- 06 May, 2014 6 commits
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Ville Syrjälä authored
We won't be calling intel_enable_primary_plane() or intel_disable_primary_plane() with the primary plane in the wrong state. So remove the useless DISPLAY_PLANE_ENABLE checks. v2: Convert the checks to WARNs instead (Daniel,Paulo) Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Ville Syrjälä authored
On ILK when we disable a particular watermark level, we must maintain the actual watermark values for that level for some time (until the next vblank possibly). Otherwise we risk underruns. In order to achieve that result we must merge the LP1+ watermarks a bit differently since we must also merge levels that are to be disabled. We must also make sure we don't overflow the fields in the watermark registers in case the calculated watermarks come out too big to fit. As early as possbile we mark all computed watermark levels as disabled if they would exceed the register maximums. We make sure to leave the actual watermarks for such levels zeroed out. Then during merging, we take the maxium values for every level, regardless if they're disabled or not. That may seem a bit pointless since at the moment all the watermark levels we merge should have their values zeroed if the level is already disabled. However soon we will be dealing with intermediate watermarks that, in addition to the new watermark values, also contain the previous watermark values, and so levels that are disabled may no longer be zeroed out. v2: Split the patch in two (Paulo) Use if() instead of & when merging ->enable (Paulo) Signed-off-by: -
Ville Syrjälä authored
When we calculate the watermarks for a pipe make sure we leave any level fully zeroed out if it would exceed any of the maximum values that fit in the registers. This will be important later when we start to use also disabled watermark levels during LP1+ merging. Signed-off-by:
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Ville Syrjälä authored
Add trace points for observing the atomic pipe update mechanism. v2: Rebased due to earlier changes v3: Pass intel_crtc instead of drm_crtc (Daniel) v4: Pass frame counter from the caller to evaded/end since the caller now always has that ready Reviewed-by:Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
Sourab Gupta <sourabgupta@gmail.com> Reviewed-by:
Akash Goel <akash.goels@gmail.com> Signed-off-by:
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Ville Syrjälä authored
Move the primary plane enable/disable to occur atomically with the sprite update that caused the primary plane visibility to change. FBC and IPS enable/disable is left to happen well before or after the primary plane change. v2: Pass intel_crtc instead of drm_crtc (Daniel) Reviewed-by:
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Ville Syrjälä authored
Add a mechanism by which we can evade the leading edge of vblank. This guarantees that no two sprite register writes will straddle on either side of the vblank start, and that means all the writes will be latched together in one atomic operation. We do the vblank evade by checking the scanline counter, and if it's too close to the start of vblank (too close has been hardcoded to 100usec for now), we will wait for the vblank start to pass. In order to eliminate random delayes from the rest of the system, we operate with interrupts disabled, except when waiting for the vblank obviously. Note that we now go digging through pipe_to_crtc_mapping[] in the vblank interrupt handler, which is a bit dangerous since we set up interrupts before the crtcs. However in this case since it's the vblank interrupt, we don't actually unmask it until some piece of code requests it. v2: preempt_check_resched() calls after local_irq_enable() (Jesse) Hook up the vblank irq stuff on BDW as well v3: Pass intel_crtc instead of drm_crtc (Daniel) Warn if crtc.mutex isn't locked (Daniel) Add an explicit compiler barrier and document the barriers (Daniel) Note the irq vs. modeset setup madness in the commit message (Daniel) v4: Use prepare_to_wait() & co. directly and eliminate vbl_received v5: Refactor intel_pipe_handle_vblank() vs. drm_handle_vblank() (Chris) Check for min/max scanline <= 0 (Chris) Don't call intel_pipe_update_end() if start failed totally (Chris) Check that the vblank counters match on both sides of the critical section (Chris) v6: Fix atomic update for interlaced modes v7: Reorder code for better readability (Chris) v8: Drop preempt_check_resched(). It's not available to modules anymore and isn't even needed unless we ourselves cause a wakeup needing reschedule while interrupts are off Reviewed-by:
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- 05 May, 2014 2 commits
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Ben Widawsky authored
All the rest of the code to enable this is in my branch. Without my branch, hitting > 32b offsets is impossible. The code has always "supported" 64b, but it's never actually been run of tested. This change doesn't actually fix anything. [1] I am not sure why X won't work yet. I do not get hangs or obvious errors. There are 3 fixes grouped together here. First is to remove the hardcoded 0 for the upper dword of the relocation. The next fix is to use a 64b value for target_offset. The final fix is to not directly apply target_offset to reloc->delta. reloc->delta is part of ABI, and so we cannot change it. As it stands, 32b is enough to represent everything we're interested in representing anyway. The main problem is, we cannot add greater than 32b values to it directly. [1] Almost all of intel-gpu-tools is not yet ready to test 64b relocations. There are a few places that expect 32b values for offsets and these all won't work. Cc: Rafael Barbalho <rafael.barbalho@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Ben Widawsky <ben@bwidawsk.net> Reviewed-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
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Ben Widawsky authored
Previously, our code only had a 32b offset value for where the batchbuffer starts. With full PPGTT, and 64b canonical GPU address space, that is an insufficient value. The code to expand is pretty straight forward, and only one platform needs to do anything with the extra bits. Signed-off-by:
Rafael Barbalho <rafael.barbalho@intel.com> Signed-off-by:
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