- 18 Jul, 2019 40 commits
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Charlene Liu authored
add dc_set_clock add dc_get_clock this is for testing and diagnostics to get/set DPPCLK and DISPCLK. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Derek Lai authored
[Why] Driver will create 0, 1, and 2 ddc engines for RV2, but some platforms used 0, 1, and 3. [How] Still allocate 4 ddc engines for RV2. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Acked-by:
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Murton Liu authored
[Why] Implementation of stereo mux register is complete, but unused. Need to call functions to write relevant configs. [How] Add function to write stereo config for enable/disable case and call in stereo control interface. Signed-off-by:
Murton Liu <murton.liu@amd.com> Reviewed-by:
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Aric Cyr authored
Signed-off-by:
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Ilya Bakoulin authored
[Why] Alpha could be improperly applied (only affecting half the frame) for some source pixel formats. [How] Change how alpha is enabled in MPC/DPP LB and change the bottom plane blend mode in MPC. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Ilya Bakoulin authored
For clarity, save the use_pitch_c logic to a bool Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Acked-by:
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Nevenko Stupar authored
Add this register for future use Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Acked-by:
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Qingqing Zhuo authored
[Why] bypass CM block and MPC ogam for debug or triage use. [How] create a new flag cm_bypass_mode, which will set both CM_CONTROL and MPCC_OGAM_MODE to bypass when set to 1. Signed-off-by:
Qingqing Zhuo <qingqing.zhuo@amd.com> Reviewed-by:
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Vitaly Prosyak authored
[Why & How] Number of 3DLUT's in MPC are not equal to number of pipes. Resource management is required. Activate on FPGA entire tm solution which includes the following :hdr multiplier, shaper, 3dlut. Signed-off-by:
Gary Kattan <Gary.Kattan@amd.com> Acked-by:
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Joshua Aberback authored
[Why] We want a debug option to disable timing sync for testing. [How] New dc debug option that must be false to call program_timing_sync Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Nikola Cornij authored
[why] As a fail-safe, in case 'set FEC_READY' DPCD write fails, a HW shadow register should be cleared and the internal FEC stat should be set to 'not ready'. This is to make sure HW settings will be consistent with FEC_READY state on the RX. Signed-off-by:
Nikola Cornij <nikola.cornij@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Krunoslav Kovac authored
[Why&How] 1. Stack usage is pretty high as fixed31_32 struct is 8 bytes and we have functions with >30 vars on the stack. 2. Optimize gamma calculation by reducing number of calls to dc_fixpt_pow Our X points are divided into 32 regions wth 16 pts each. Each region is 2x the previous, meaning x[i] = 2*x[i-16] for i>=16. Using (2x)^gamma = 2^gamma * x^gamma, we can recursively compute powers of gamma, we just need first 16 pts to start it up. dc_fixpt_pow() is expensive, it computes x^y by doing exp(y*logx) Exp is done by Taylor series approximation, and log by Newton-like approximation that also uses exp internally. In short, it's significantly heavier than run-of-the-mill addition/subtraction/multiply. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Eric Yang authored
[Why] Seamless boot optimization removed proper front end power off sequence. In driver disable enable case, this causes driver to power gate hubp and dpp while there is still memory fetching going on, this can cause invalid memory requests to be generated which will hang data fabric. [How] Put back proper front end power off sequence Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Signed-off-by:
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Nikola Cornij authored
[why] Right now we FEC_READY is set only before the final link training, i.e. at mode set time. This means FEC_READY won't be set when doing link training as a response to HPD. It also fails UCD400 FEC test in DP compliance. [how] Move FEC_READY setup to link training. Signed-off-by:
Abdoulaye Berthe <Abdoulaye.Berthe@amd.com> Acked-by:
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Eric Bernstein authored
Use helper to determine if HDMI signal when processing avmute. Signed-off-by:
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Murton Liu authored
[Why] Logic & structures for generic regs does not exist in DC currently. [How] Implement register masks/shifts and relevant functions for generic mux, similar to existing HPD and DDC objects. V2: fix includes for kalloc/free (Alex) Signed-off-by:
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Alvin Lee authored
[why] In pipe split issue occurs when we program immediate flip while vsync flip is pending [how] Don't program immediate flip until flip is no longer pending Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jaehyun Chung <Jaehyun.Chung@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Fatemeh Darbehani authored
[Why] Some display's hsync width is lower than the minimum dcn20 is set to support right now. This will cause optc1_validate_timing to fail which eventually will result in wrong set mode. This was set to 8 as per HW team's request for no valid reason. [How] Changing min_h_sync_width to 4 will let us validate timing for preffered mode and light up the headset. This change was made to Vega 10 before for a similar issue. Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
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Alvin Lee authored
[why] We initialize pp_smu twice [how] Remove second initialization of pp_smu Signed-off-by:
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Su Sung Chung authored
[why] dcn20_clk_mgr_construct was not initializing pp_smu, and PME call gets filtered out by the null check [how] initialize pp_smu dcn20_clk_mgr_construct Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Tai Man authored
[Why] On some platforms, the encoder id 3 is not populated. So the encoders are not stored in right order as index (id: 0, 1, 2, 4, 5) at pool. This would cause encoders id 4 & id 5 to fail when finding corresponding audio device, defaulting to the first available audio device. As result, we cannot stream audio into two DP ports with encoders id 4 & id 5. [How] It need to create enough audio device objects (0 - 5) to perform matching. Then use encoder engine id to find matched audio device. Signed-off-by:
Tai Man <taiman.wong@amd.com> Reviewed-by:
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Harry Wentland authored
[Why] link_stream is never NULL here as we've dereferenced it a couple lines before and have done so for a couple months now. [How] - Drop the NULL check. - Initialize where we know link_stream is non-NULL Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Charlene Liu authored
[Description] Do not fill Null packet in the blank period for new packet gen This is based on HW IP team recommended default setting change. Signed-off-by:
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Zi Yu Liao authored
[why] When the system is going into suspend, set_backlight gets called after the eDP got blanked. Since smooth brightness is enabled, the driver will make a call into the DMCU to ramp the brightness. The DMCU would try to enable ABM to do so. But since the display is blanked, this ends up causing ABM1_ACE_DBUF_REG_UPDATE_PENDING to get stuck at 1, which results in a dead lock in the DMCU firmware. [how] Disable brightness ramping when the eDP display is blanked. Signed-off-by:
Zi Yu Liao <ziyu.liao@amd.com> Reviewed-by:
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Alvin Lee authored
[Why] When we recover from hang, we do not want to skip the audio enable call. [How] Disable audio in dc_reinitialize_hardware Signed-off-by:
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Nikola Cornij authored
[why] DSC should be powered-on only on as-needed basis, i.e. if the mode requires it [how] Loop over all the DSCs at driver init time and power-gate each Signed-off-by:
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Dmytro Laktyushkin authored
Current default is sufficient for a flag that does not change. Signed-off-by:
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Derek Lai authored
[Why] When launch D10.2, driver will write DPCD 0x107 with 0x00 [How] Read MAX_DOWNSPREAD (0x0003h) then keep in current link settings Signed-off-by:
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Ilya Bakoulin authored
[Why] A hubp pointer was being passed to DCN1 functions, which expect the enclosing structure (for the purpose of container_of macros) to be dcn10_hubp, but the actual type was dcn20_hubp. [How] Copy existing DCN1 functions and alter them slightly for use with dcn20_hubp. Signed-off-by:
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Ilya Bakoulin authored
Before accessing it's vtable, check that stream_encoder is non-null. Signed-off-by:
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Ilya Bakoulin authored
[Why] Need to implement register programming for HDR dynamic metadata transmission and tests. Signed-off-by:
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Aric Cyr authored
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SivapiriyanKumarasamy authored
[WHY] Currently we don't wait for blacklight programming completion in DMCU when setting backlight level. Some sequences such as PSR static screen event trigger reprogramming requires it to be complete. [How] Add generic wait for dmcu command completion in set backlight level. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
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Dingchen Zhang authored
[Why] We need to check the pipe crc source through debugfs for bypass mode test. [How] add implementation of amdgpu_dm_crtc_get_crc_sources and hook into drm_crtc callback get_crc_sources. Signed-off-by:
Dingchen Zhang <dingchen.zhang@amd.com> Reviewed-by:
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Dingchen Zhang authored
[Why] We need to compare DPRX CRCs with framebuffer CRCs for digital bypass mode. [How] Hook into DRM to grab DP receiver CRCs through drm_dp_start_crc. Signed-off-by:
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Julian Parkin authored
[Why] Hardware docs state that we must wait until the GPUVM context is ready after programming it. [How] Poll until the valid bit of PAGE_TABLE_BASE_ADDR_LO32 is set to 1 after programming it. v2: fix include for udelay (Alex) Signed-off-by:
Julian Parkin <julian.parkin@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Specifically to one panel, TCON is able to accept active video signal quickly, but the Source Driver requires 2-3 frames of extra time. It is a Panel issue since TCON needs to take care of all Sink requirements including Source Driver. But in this case it does not. Customer is asking to add fixed T7 delay as panel workaround. [How] Add monitor specific patch to add T7 delay Signed-off-by:
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Dmytro Laktyushkin authored
This change adds EMP packet programming for enabling dsc with hdmi. The packets are structured according to VESA HDMI 2.1x r2 spec, section 10.10.2.2. Signed-off-by:
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Su Sung Chung authored
[why] for 2 purposes: 1. get raw register value dumped on the log, which will make it easier to talk to other team who only knows about the register 2. enable other HW to be able to use the same interface as raven to log clock register data Signed-off-by:
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