- 28 Apr, 2017 2 commits
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Marek Vasut authored
Add driver for the GPIO block in the ROHM BD9571MWV-W MFD PMIC. This block is pretty trivial and supports setting GPIO direction as Input/Output and in case of Output, supports setting value. Signed-off-by:
Marek Vasut <marek.vasut+renesas@gmail.com> Cc: linux-gpio@vger.kernel.org Cc: Geert Uytterhoeven <geert+renesas@glider.be> Cc: Linus Walleij <linus.walleij@linaro.org> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Signed-off-by:
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Kuppuswamy Sathyanarayanan authored
According to Whiskey Cove PMIC spec, bit 7 of GPIOIRQ0_REG belongs to battery IO. So we should skip this bit when checking for GPIO IRQ pending status. Otherwise, wcove_gpio_irq_handler() might go into the infinite loop until IRQ "pending" status becomes 0. This patch fixes this issue. Signed-off-by:
Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by:
Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by:
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- 24 Apr, 2017 12 commits
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Anders Darander authored
The TCA9554 is similar to the PCA9554. Update the DT binding docs. Signed-off-by:
Anders Darander <anders@chargestorm.se> Signed-off-by:
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Anders Darander authored
The TCA9554 doesn't work with the pcf857x driver, trying to change the direction gives a NAK bailout error. TCA9554 is similar to the PCA9554, thus change the driver. Signed-off-by:
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Charles Keepax authored
The logic to check if the pin is an input or output whilst testing if we need to read the register value from the hardware or not is currently inverted. Remove the erroneous not from the if statement. Fixes: 11598d17 ("gpio: arizona: Correct handling for reading input GPIOs") Signed-off-by:
Charles Keepax <ckeepax@opensource.wolfsonmicro.com> Signed-off-by:
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Nandor Han authored
Add the XRA1403 DTS binding documentation. Signed-off-by:
Nandor Han <nandor.han@ge.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Nandor Han authored
Add Exar Corporation to vendors list. Signed-off-by:
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Kuppuswamy Sathyanarayanan authored
Whiskey cove PMIC has three GPIO banks with total number of 13 GPIO pins. But when checking for the pending status, for_each_set_bit() uses bit width of 7 and hence it only checks the status for first 7 GPIO pins missing to check/clear the status of rest of the GPIO pins. This patch fixes this issue. Signed-off-by:
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Jisheng Zhang authored
Commit 67809b97 ("GPIO: gpio-dwapb: Change readl&writel to dwapb_read&dwapb_write") missed this readl_relaxed() usage, I'm not sure the reason, maybe for performance reason? But if we do care the performance, we could use the relaxed io in dwapb_read and dwapb_write. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Signed-off-by:
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Andrew Jeffery authored
As per the datasheet, manage the IO and value states to implement open-source/open-drain, but do this by falling back to gpiolib's emulation. This commit simply makes the behaviour explicit for clarity, rather than relying on the implicit return of -ENOTSUPP to trigger the emulation. Signed-off-by:
Andrew Jeffery <andrew@aj.id.au> Signed-off-by:
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Andrew Jeffery authored
Each GPIO in the Aspeed GPIO controller can choose one of four input debounce states: to disable debouncing for an input, or select from one of three programmable debounce timer values. Each GPIO in a four-bank-set is assigned one bit in each of two debounce configuration registers dedicated to the set, and selects a debounce state by configuring the two bits to select one of the four options. The limitation on debounce timer values is managed by mapping offsets onto a configured timer value and keeping count of the number of users a timer has. Timer values are configured on a first-come-first-served basis. A small twist in the hardware design is that the debounce configuration register numbering is reversed with respect to the binary representation of the debounce timer of interest (i.e. debounce register 1 represents bit 1, and debounce register 2 represents bit 0 of the timer numbering). Tested on an AST2500EVB with additional inspection under QEMU's romulus-bmc machine. Signed-off-by:
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Andrew Jeffery authored
We need a reference to the HPLL to calculate debounce cycles. If the clocks property is not supplied in the GPIO node then the consumer should deny any debounce requests. Signed-off-by:
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Andrew Jeffery authored
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Andrew Lunn authored
Armada 370/XP devices can 'blink' GPIO lines with a configurable on and off period. This can be modelled as a PWM. However, there are only two sets of PWM configuration registers for all the GPIO lines. This driver simply allows a single GPIO line per GPIO chip of 32 lines to be used as a PWM. Attempts to use more return EBUSY. Due to the interleaving of registers it is not simple to separate the PWM driver from the GPIO driver. Thus the GPIO driver has been extended with a PWM driver. Signed-off-by:
Andrew Lunn <andrew@lunn.ch> URL: https://patchwork.ozlabs.org/patch/427287/ URL: https://patchwork.ozlabs.org/patch/427295/ [Ralph Sennhauser: * Port forward * Merge PWM portion into gpio-mvebu.c * Switch to atomic PWM API * Add new compatible string marvell,armada-370-xp-gpio * Update and merge documentation patch * Update MAINTAINERS] Signed-off-by:
Ralph Sennhauser <ralph.sennhauser@gmail.com> Tested-by:
Thierry Reding <thierry.reding@gmail.com> Acked-by:
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- 13 Apr, 2017 1 commit
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Thierry Reding authored
Interrupt numbers are never negative, zero serves as the special invalid value. Signed-off-by:
Thierry Reding <treding@nvidia.com> Signed-off-by:
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- 07 Apr, 2017 3 commits
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Marty Plummer authored
Add F71889A GPIO support. Fintek F71889A is a SuperIO. It contains HWMON/GPIO/Serial Ports. Datasheet: http://www.alldatasheet.com/datasheet-pdf/pdf/459076/FINTEK/F71889A.html Its virtually identical to the F71889F superio as far as gpios go. One oddity is GPIO2 at index 0xD0; the datasheet only lists gpio's 7-5, but it logically seems that it should continue down to 0. I'm not sure if the driver can handle gpios that are shifted away from index 0 as it currently stands. Signed-off-by:
Marty Plummer <netz.kernel@gmail.com> Signed-off-by:
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Laxman Dewangan authored
Currently, the GPIO interface is said to Open Drain if it is Single Ended and active LOW. Similarly, it is said as Open Source if it is Single Ended and active HIGH. The active HIGH/LOW is used in the interface for setting the pin state to HIGH or LOW when enabling/disabling the interface. In Open Drain interface, pin is set to HIGH by putting pin in high impedance and LOW by driving to the LOW. In Open Source interface, pin is set to HIGH by driving pin to HIGH and set to LOW by putting pin in high impedance. With above, the Open Drain/Source is unrelated to the active LOW/HIGH in interface. There is interface where the enable/disable of interface is ether active LOW or HIGH but it is Open Drain type. Hence decouple the Open Drain with Single Ended + Active LOW and Open Source with Single Ended + Active HIGH. Adding different flag for the Open Drain/Open Source which is valid only when Single ended flag is enabled. Signed-off-by:
Laxman Dewangan <ldewangan@nvidia.com> Signed-off-by:
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Charles Keepax authored
The GPIO register is cached since all the configuration resides within it, however, this means for input GPIOs the driver will not return the actual state but the last value written to the register cache. To correct this in the case of reading an input GPIO resume the CODEC and drop the cache for the input register to ensure an actual hardware read takes place. Signed-off-by:
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- 28 Mar, 2017 3 commits
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Julia Cartwright authored
The 104-idi-48 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
Julia Cartwright <julia@ni.com> Acked-by:
William Breathitt Gray <vilhelm.gray@gmail.com> Signed-off-by:
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Julia Cartwright authored
The pci-idio-16 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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Julia Cartwright authored
The 104-idio-16 gpio driver currently implements an irq_chip for handling interrupts; due to how irq_chip handling is done, it's necessary for the irq_chip methods to be invoked from hardirq context, even on a a real-time kernel. Because the spinlock_t type becomes a "sleeping" spinlock w/ RT kernels, it is not suitable to be used with irq_chips. A quick audit of the operations under the lock reveal that they do only minimal, bounded work, and are therefore safe to do under a raw spinlock. Signed-off-by:
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- 24 Mar, 2017 5 commits
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Russell King authored
Add support for mapping gpio-reg gpios to interrupts. This may be a non-linear mapping - some gpios in the register may not even have corresponding interrupts associated with them, so we need to pass an array. Signed-off-by:
Russell King <rmk+kernel@armlinux.org.uk> Signed-off-by:
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Russell King authored
Add a simple, generic, single register fixed-direction GPIO driver. This is able to support a single register with a mixture of inputs and outputs. This is different from gpio-mmio and gpio-74xx-mmio: * gpio-mmio doesn't allow a fixed direction, it assumes there is always a direction register. * gpio-74xx-mmio only supports all-in or all-out setups * gpio-74xx-mmio is DT only, this needs to support legacy too * they don't double-read when getting the GPIO value, as required by some implementations that this driver supports * we need to always do 32-bit reads, which bgpio doesn't guarantee * the current output state may not be readable from the hardware register - reading may reflect input status but not output status. Signed-off-by:
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Russell King authored
Allow gpiolib to read back the current IO direction configuration by implementing the .get_direction callback. This, in part, allows debugfs to report the complete true hardware state rather than the software state. Signed-off-by:
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Russell King authored
Use IO accessors to access the SA1100 registers rather than accessing them directly. Signed-off-by:
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Russell King authored
Use sa11x0_gpio_set_wake() to set the PWER register, as provided by Dmitry some time back. Signed-off-by:
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- 23 Mar, 2017 7 commits
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Andy Shevchenko authored
The mentioned flags are dedicated solely for consumer API. Replace them by explicit values. Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> [Made a !bang clamp to (0,1) instead of infix ? operator] Signed-off-by:
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Andy Shevchenko authored
Switch to use managed variant of acpi_dev_add_driver_gpios() to simplify error path and fix potentially wrong assignment if ->probe() fails. While here, add a debug message in case assignment fails to allow user see the cause of a potential issue. Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by:
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Andy Shevchenko authored
GPIO ACPI library is going to be stricter about resources, thus, expand comment regarding "reset" GPIO resource in this driver to clarify its usage in ACPI case. Signed-off-by:
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Andy Shevchenko authored
For sake of better maintenance sort the headers by alphabetical order. Signed-off-by:
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Andy Shevchenko authored
Introduce ->get_direction() callback for the driver. Signed-off-by:
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Ralph Sennhauser authored
Use the BIT macro instead of explicitly shifting bits for some added clarity. Signed-off-by:
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Nathan Sullivan authored
The GPIO-based NAND controller on National Instruments 169445 hardware exposes a set of simple lines for the control signals. Signed-off-by:
Nathan Sullivan <nathan.sullivan@ni.com> Signed-off-by:
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- 22 Mar, 2017 3 commits
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Linus Walleij authored
This just deletes the Moxa ART driver and replaces it with the more versatile Faraday FTGPIO010 driver. Make this default on for ARCH_GEMINI and ARCH_MOXART so we do not get Kconfig glitches. Tested-by:
Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by:
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Linus Walleij authored
The Gemini driver is actually a driver for the Faraday Technology FTGPIO010 IP block. We rename the driver and the Kconfig symbol and put in a a new compatible string for the Moxa ART SoC that is also using this IP block. Tested-by:
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Linus Walleij authored
The DT bindings assumed that this IP block was coming from Cortina Systems, which turns out not to be true. It is a standard IP block from Faraday Technology and also used in the Moxa moxart SoC. We augment the bindings to cover all existing parts and rename it after the IP block. This involves deleting the old Moxa bindings that now are contained in this binding. Cc: devicetree@vger.kernel.org Cc: Jonas Jensen <jonas.jensen@gmail.com> Acked-by:
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- 16 Mar, 2017 4 commits
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Ralph Sennhauser authored
A modern compiler should know better when to inline, so drop the inline keywords. Signed-off-by:
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Ralph Sennhauser authored
Fix whitespace errors missed by checkpatch. Signed-off-by:
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Ralph Sennhauser authored
Fix whitespace errors reported by checkpatch. Signed-off-by:
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Ralph Sennhauser authored
Use unsigned int instead of plain unsigned as reported by checkpatch. Signed-off-by:
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