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- 20 May, 2018 1 commit
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Sergei Shtylyov authored
The R-Car V3H (AKA R8A77980) GEther controller adds the DMA burst mode bit (NBST) in EDMR and the manual tells to always set it before doing any DMA. Based on the original (and large) patch by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 01 Apr, 2018 1 commit
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Sergei Shtylyov authored
The commit 6ded2865 ("sh_eth: Fix RX recovery on R-Car in case of RX ring underrun") added a check for an bad RDFAR offset in sh_eth_rx(), so that the code could work on the R-Car Ether controllers which don't have this register (and TDFAR), then the commit 3365711d ("sh_eth: WARN on access to a register not implemented in a particular chip") replaced offset 0 with 0xffff. Adding/checking the 'no_xdfar' bit field in the 'struct sh_eth_cpu_data' instead results in less object code... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 26 Mar, 2018 5 commits
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Sergei Shtylyov authored
GEther controllers have CERCR/CEECR instead of CNDCR on the others. Currently we are calling sh_eth_is_gether() in order to check for this, however it would be simpler to check the new 'cexcr' bitfield in the 'struct sh_eth_cpu_data'; then we'd be able to remove sh_eth_is_gether() as there would be no callers left... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
RZ/A1H (R7S72100) Ether controller doesn't seem to have the TX counter registers like TROCR/CDCR/LCCR (or at least they are still undocumented like some TSU registers), so we bail out of sh_eth_get_stats() early in this case. Currently we are calling sh_eth_is_rz_fast_ether() in order to check for this, but it would be simpler to check the new 'no_tx_cntrs' bitfield in the 'struct sh_eth_cpu_data'; then we'd be able to remove sh_eth_is_rz_fast_ether() as there would be no callers left... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
The GEther-like controllers have writeable RDFAR/TDFAR, on the others they are read-only or just absent (on R-Car). Currently we are calling sh_eth_is_{gether|rz_fast_ether}() in order to check if these registers can be written to, however it would be simpler to check the new 'xdfar_rw' bitfield in the 'struct sh_eth_cpu_data'... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
sh_eth_get_edtrr_trns() returns the value to be written to EDTRR in order to start TX DMA -- this value is different between the GEther-like and the other controllers. We can replace this function (and thus get rid of the calls to sh_eth_is_{gether|rz_fast_ether}() by it) with a new field 'edtrr_trns' in the 'struct sh_eth_cpu_data'. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
sh_eth_reset() performs a software reset which is implemented in a completely different way for the GEther-like controllers vs the other controllers due to a different layout of EDMR (and other factors) -- it therefore makes sense to convert this function to a mandatory sh_eth_cpu_data::soft_reset() method and thus get rid of the runtime controller type check via sh_eth_is_{gether|rz_fast_ether}(). Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 27 Feb, 2018 1 commit
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Sergei Shtylyov authored
We have uninlined the sh_eth_{read|write}() functions introduced in the commit 4a55530f ("net: sh_eth: modify the definitions of register"). Now remove *inline* from sh_eth_tsu_{read|write}() as well and move these functions from the header to the driver itself. This saves 684 more bytes of object code (ARM gcc 4.8.5)... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 26 Feb, 2018 2 commits
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Sergei Shtylyov authored
It appears that the single port Ether controllers having TSU (like SH7734/ R8A7740) need the same kind of treating in sh_eth_tsu_init() as R7S72100 currently has -- they also don't have the TSU registers related e.g. to passing the frames between ports. Add the 'sh_eth_cpu_data::dual_port' flag and use it as a new criterion for taking a "short path" in the TSU init sequence in order to avoid writing to the non-existent registers... Fixes: f0e81fec ("net: sh_eth: Add support SH7734") Fixes: 73a0d907 ("net: sh_eth: add support R8A7740") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
The TSU_QTAG0/1 registers found in the Gigabit Ether controllers actually have the same long name as the TSU_QTAGM0/1 registers in the early Ether controllers: Qtag Addition/Deletion Set Register (Port 0/1 to 1/0); thus there's no need to make a difference in sh_eth_tsu_init() between those controllers. Unfortunately, we can't just remove TSU_QTAG0/1 from the register *enum* because that would break the ethtool register dump... Fixes: b0ca2a21 ("sh_eth: Add support of SH7763 to sh_eth") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 31 Jan, 2017 2 commits
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Sergei Shtylyov authored
Renesas SH77{34|63} manuals describe more EESIPR bits than the current driver. Declare the new bits with the end goal of using the bit names instead of the bare numbers for the 'sh_eth_cpu_data::eesipr_value' initializers... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
Since the commit b0ca2a21 ("sh_eth: Add support of SH7763 to sh_eth") the *enum* declaring the EESIPR bits (interrupt mask) went out of sync with the *enum* declaring the EESR bits (interrupt status) WRT bit naming and formatting. I'd like to restore the consistency by using EESIPR as the bit name prefix, renaming the *enum* to EESIPR_BIT, and (finally) renaming the bits according to the available Renesas SH77{34|63} manuals; additionally, reconstruct couple names using the EESR bit declaration above... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 09 Jan, 2017 4 commits
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Niklas Söderlund authored
Add generic functionality to support Wake-on-LAN using MagicPacket which are supported by at least a few versions of sh_eth. Only add functionality for WoL, no specific sh_eth versions are marked to support WoL yet. WoL is enabled in the suspend callback by setting MagicPacket detection and disabling all interrupts expect MagicPacket. In the resume path the driver needs to reset the hardware to rearm the WoL logic, this prevents the driver from simply restoring the registers and to take advantage of that sh_eth was not suspended to reduce resume time. To reset the hardware the driver closes and reopens the device just like it would do in a normal suspend/resume scenario without WoL enabled, but it both closes and opens the device in the resume callback since the device needs to be open for WoL to work. One quirk needed for WoL is that the module clock needs to be prevented from being switched off by Runtime PM. To keep the clock alive the suspend callback need to call clk_enable() directly to increase the usage count of the clock. Then when Runtime PM decreases the clock usage count it won't reach 0 and be switched off. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: David S. Miller <davem@davemloft.net>
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Niklas Söderlund authored
This bit was wrongly named due to a typo, Sergei checked the SH7734/63 manuals and this bit should be named MPDE. Suggested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
The 'struct sh_eth_cpu_data' field indicating the "intelligent checksum" support was misnamed 'hw_crc' -- rename it to 'hw_checksum'. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
After checking all the available manuals, I have enough information to conclude that the 'shift_rd0' flag is only relevant for the Ether cores supporting so called "intelligent checksum" (and hence having CSMR) which is indicated by the 'hw_crc' flag. Since all the relevant SoCs now have both these flags set, we can at last get rid of the former flag... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 04 Jan, 2017 1 commit
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Sergei Shtylyov authored
The E-MAC interrupt (EESR.ECI) is not always caused by an error condition, so it really shouldn't be handled by sh_eth_error(). Factor out the E-MAC interrupt handler, sh_eth_emac_interrupt(), removing the ECI bit from the EESR's values throughout the driver... Update Cogent Embedded's copyright and clean up the whitespace in Renesas' copyright, while at it... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 11 Aug, 2016 1 commit
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Philippe Reynes authored
The private structure contain a pointer to phydev, but the structure net_device already contain such pointer. So we can remove the pointer phy_dev in the private structure, and update the driver to use the one contained in struct net_device. Signed-off-by: Philippe Reynes <tremyfr@gmail.com> Tested-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 26 Apr, 2016 1 commit
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Sergei Shtylyov authored
The Renesas RZ/A1H manual names the software reset bit in the software reset register (ARSTR) ARST which makes a bit more sense than the ARSTR_ARSTR name used now by the driver -- rename the latter to ARSTR_ARST. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 04 Jan, 2016 1 commit
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Sergei Shtylyov authored
Commit 71557a37 ("[netdrvr] sh_eth: Add SH7619 support") added support for the big-endian EDMAC descriptors. However, it was never used and never worked right until the recent driver fixes. I think we now can just remove this support, it was only burdening the driver from the start. It should be easy to do without disturbing the SH platform code, at least for now... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 22 Dec, 2015 1 commit
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Sergei Shtylyov authored
Commit 1299653a ("sh_eth: fix descriptor access endianness") only addressed the 32-bit buffer address field byte-swapping but the driver still accesses 16-bit frame/buffer length descriptor fields without the necessary byte-swapping -- which should affect the big-endian kernels. In order to be able to use {cpu|edmac}_to_{edmac|cpu}(), we need to declare the RX/TX descriptor word 1 as a 32-bit field and use shifts/masking to access the 16-bit subfields (which gets rid of the ugly #ifdef'ery too)... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 14 Dec, 2015 1 commit
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Sergei Shtylyov authored
Commit 3365711d ("sh_eth: WARN on access to a register not implemented in in a particular chip") added WARN_ON() to sh_eth_{read|write}(), thus making it unacceptable for these functions to be *inline* anymore. Remove *inline* and move the functions from the header to the driver itself. Below is our code economy with ARM gcc 4.7.3: $ size drivers/net/ethernet/renesas/sh_eth.o{~,} text data bss dec hex filename 32489 1140 0 33629 835d drivers/net/ethernet/renesas/sh_eth.o~ 25413 1140 0 26553 67b9 drivers/net/ethernet/renesas/sh_eth.o Suggested-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 03 Nov, 2015 1 commit
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Sergei Shtylyov authored
The correct name of the RX descriptor 0 bit 30 is RDLE (receive descriptor list end), not RDEL. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 04 Mar, 2015 2 commits
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Ben Hutchings authored
There are many different sets of registers implemented by the different versions of this controller, and we can only expect this to get more complicated in future. Limit how much ethtool needs to know by including an explicit bitmap of which registers are included in the dump, allowing room for future growth in the number of possible registers. As I don't have datasheets for all of these, I've only included registers that are: - defined in all 5 register type arrays, or - used by the driver, or - documented in the datasheet I have Add one new capability flag so we can tell whether the RTRATE register is implemented. Delete the TSU_ADRL0 and TSU_ADR{H,L}31 definitions, as they weren't used and the address table is already assumed to be contiguous. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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Ben Hutchings authored
Currently we may silently read/write a register at offset 0. Change this to WARN and then ignore the write or read-back all-ones. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 27 Jan, 2015 1 commit
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Ben Hutchings authored
In order to stop the RX path accessing the RX ring while it's being stopped or resized, we clear the interrupt mask (EESIPR) and then call free_irq() or synchronise_irq(). This is insufficient because the interrupt handler or NAPI poller may set EESIPR again after we clear it. Also, in sh_eth_set_ringparam() we currently don't disable NAPI polling at all. I could easily trigger a crash by running the loop: while ethtool -G eth0 rx 128 && ethtool -G eth0 rx 64; do echo -n .; done and 'ping -f' toward the sh_eth port from another machine. To fix this: - Add a software flag (irq_enabled) to signal whether interrupts should be enabled - In the interrupt handler, if the flag is clear then clear EESIPR and return - In the NAPI poller, if the flag is clear then don't set EESIPR - Set the flag before enabling interrupts in sh_eth_dev_init() and sh_eth_set_ringparam() - Clear the flag and serialise with the interrupt and NAPI handlers before clearing EESIPR in sh_eth_close() and sh_eth_set_ringparam() After this, I could run the loop for 100,000 iterations successfully. Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 15 Jan, 2015 1 commit
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Geert Uytterhoeven authored
Replace "unsigned long" by "u32" when handling 32-bit register data. A.o., this saves 11 * 36 bytes in the static sh_eth_cpu_data structures when compiling for 64-bit. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 09 Jan, 2015 1 commit
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Nobuhiro Iwamatsu authored
TRSCER register is configured differently by SoCs. TRSCER of R-Car Gen2 is RINT8 bit only valid, other bits are reserved bits. This removes access to TRSCER register reserve bit by adding variable trscer_err_mask to sh_eth_cpu_data structure, set the register information to each SoCs. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 30 Nov, 2014 2 commits
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Mitsuhiro Kimura authored
This resolves the following bug which can be reproduced by building the kernel with CONFIG_DEBUG_ATOMIC_SLEEP=y and reading network statistics while the network interface is down. e.g.: ifconfig eth0 down cat /sys/class/net/eth0/statistics/tx_errors ---- [ 1238.161349] BUG: sleeping function called from invalid context at drivers/base/power/runtime.c:952 [ 1238.188279] in_atomic(): 1, irqs_disabled(): 0, pid: 1388, name: cat [ 1238.207425] CPU: 0 PID: 1388 Comm: cat Not tainted 3.10.31-ltsi-00046-gefa0b46 #1087 [ 1238.230737] Backtrace: [ 1238.238123] [<c0012e64>] (dump_backtrace+0x0/0x10c) from [<c0013000>] (show_stack+0x18/0x1c) [ 1238.263499] r6:000003b8 r5:c06160c0 r4:c0669e00 r3:00404000 [ 1238.280583] [<c0012fe8>] (show_stack+0x0/0x1c) from [<c04515a4>] (dump_stack+0x20/0x28) [ 1238.304631] [<c0451584>] (dump_stack+0x0/0x28) from [<c004970c>] (__might_sleep+0xf8/0x118) [ 1238.329734] [<c0049614>] (__might_sleep+0x0/0x118) from [<c02465ac>] (__pm_runtime_resume+0x38/0x90) [ 1238.357170] r7:d616f000 r6:c049c458 r5:00000004 r4:d6a17210 [ 1238.374251] [<c0246574>] (__pm_runtime_resume+0x0/0x90) from [<c029b1c4>] (sh_eth_get_stats+0x44/0x280) [ 1238.402468] r7:d616f000 r6:c049c458 r5:d5c21000 r4:d5c21000 [ 1238.419552] [<c029b180>] (sh_eth_get_stats+0x0/0x280) from [<c03ae39c>] (dev_get_stats+0x54/0x88) [ 1238.446204] r5:d5c21000 r4:d5ed7e08 [ 1238.456980] [<c03ae348>] (dev_get_stats+0x0/0x88) from [<c03c677c>] (netstat_show.isra.15+0x54/0x9c) [ 1238.484413] r6:d5c21000 r5:d5c21238 r4:00000028 r3:00000001 [ 1238.501495] [<c03c6728>] (netstat_show.isra.15+0x0/0x9c) from [<c03c69b8>] (show_tx_errors+0x18/0x1c) [ 1238.529196] r7:d5f945d8 r6:d5f945c0 r5:c049716c r4:c0650e7c [ 1238.546279] [<c03c69a0>] (show_tx_errors+0x0/0x1c) from [<c023963c>] (dev_attr_show+0x24/0x50) [ 1238.572157] [<c0239618>] (dev_attr_show+0x0/0x50) from [<c010c148>] (sysfs_read_file+0xb0/0x140) [ 1238.598554] r5:c049716c r4:d5c21240 [ 1238.609326] [<c010c098>] (sysfs_read_file+0x0/0x140) from [<c00b9ee4>] (vfs_read+0xb0/0x13c) [ 1238.634679] [<c00b9e34>] (vfs_read+0x0/0x13c) from [<c00ba0ac>] (SyS_read+0x44/0x74) [ 1238.657944] r8:bef45bf0 r7:00000000 r6:d6ac0600 r5:00000000 r4:00000000 [ 1238.678172] [<c00ba068>] (SyS_read+0x0/0x74) from [<c000eec0>] (ret_fast_syscall+0x0/0x30) ---- Signed-off-by: Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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Mitsuhiro Kimura authored
In the current driver, allocation size of skb does not care the alignment adjust after allocation. And also, in the current implementation, buffer alignment method by sh_eth_set_receive_align function has a bug that this function displace buffer start address forcedly when the alignment is corrected. In the result, tail of the skb will exceed allocated area and kernel panic will be occurred. This patch fix this issue. Signed-off-by: Mitsuhiro Kimura <mitsuhiro.kimura.kc@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 04 Jun, 2014 1 commit
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Ben Dooks authored
The current behaviour of the sh_eth driver is not to use the RNC bit for the receive ring. This means that every packet recieved is not only generating an IRQ but it also stops the receive ring DMA as well until the driver re-enables it after unloading the packet. This means that a number of the following errors are generated due to the receive packet FIFO overflowing due to nowhere to put packets: net eth0: Receive FIFO Overflow Since feedback from Yoshihiro Shimoda shows that every supported LSI for this driver should have the bit enabled it seems the best way is to remove the RMCR default value from the per-system data and just write it when initialising the RMCR value. This is discussed in the message (http://www.spinics.net/lists/netdev/msg284912.html). I have tested the RMCR_RNC configuration with NFS root filesystem and the driver has not failed yet. There are further test reports from Sergei Shtylov and others for both the R8A7790 and R8A7791. There is also feedback fron Cao Minh Hiep[1] which reports the same issue in (http://comments.gmane.org/gmane.linux.network/316285) showing this fixes issues with losing UDP datagrams under iperf. Tested-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Acked-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 13 Feb, 2014 1 commit
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Sergei Shtylyov authored
The driver #define's and uses ETHERSMALL macro for the minimum Ethernet frame size for which we have a standard macro ETH_ZLEN. Use the latter instead of the home-grown one. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 18 Jan, 2014 1 commit
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Simon Horman authored
The r7s72100 SoC includes a fast ethernet controller. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Acked-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 04 Jan, 2014 1 commit
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Sergei Shtylyov authored
Running 'scripts/checkpatch.pl' on the driver files gives numerous warnings: - block comments using empty /* line; - unneeded \ at end of lines; - message string split across lines; - use of __attribute__((aligned(n))) instead of __aligned(n) macro; - use of __attribute__((packed)) instead of __packed macro. Additionally, running 'scripts/checkpatch.pl --strict' gives more complaints: - including the paragraph about writing to FSF into the heading comment; - alignment not matching open paren; - multiple assignments on one line; - use of CamelCase names; - missing {} on one of the *if* arms where another has them; - spinlock definition without a comment. While fixing these, also do some more style cleanups: - remove useless () around expressions; - add {} around multi-line *if* operator's arm; - remove space before comma; - add spaces after /* and before */; - properly align continuation lines of broken up expressions; - realign comments to the structure fields. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 23 Oct, 2013 1 commit
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Sergei Shtylyov authored
Declare 'enum RMCR_BIT' containing the single member for the RMCR.RNC bit and replace bare numbers in the driver by this mnemonic. Suggested-by: David Miller <davem@davemloft.net> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 21 Aug, 2013 2 commits
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Sergei Shtylyov authored
Now that the 'register_type' field of the 'sh_eth' driver's platform data is not used by the driver anymore, it's time to remove it and its initializers from the SH platform code. Also move *enum* declaring values for this field from <linux/sh_eth.h> to the local driver's header file as they're only needed by the driver itself now... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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Sergei Shtylyov authored
The register layout is a SoC characteristic, so it's wrong that it's stored in the otherwise board specific platform data. Add 'register_type' field to 'struct sh_eth_cpu_data', initialize it properly for each SoC, and read it from this structure instead of the platfrom data from now on... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 24 Jul, 2013 1 commit
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Simon Horman authored
This register is prsent on the r8a7790 SoC. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 24 Jun, 2013 1 commit
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Sergei Shtylyov authored
EESR.RFE (receive FIFO overflow) interrupt is enabled by the driver on all SoCs and sh_eth_error() handles it but it's not present in any initializer/assignment of the 'eesr_err_check' field of 'struct sh_eth_cpu_data'. This leads to that interrupt not being handled and cleared, and finally to disabling IRQ and the driver being non-functional. Modify DEFAULT_EESR_ERR_CHECK macro and all explicit initializers of the above mentioned field to contain the EESR.RFE bit. Remove useless backslashes from the initializers, while at it. Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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- 20 Jun, 2013 1 commit
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Sergei Shtylyov authored
The only R8A7740 specific #ifdef hindering ARM multiplatform build is left in sh_eth_rx(): it covers the code shifting Rx buffer descriptor word 0 by 16. Get rid of the #ifdef by adding 'shift_rd0' field to the 'struct sh_eth_cpu_data', making the shift dependent on it, and setting it to 1 for the R8A7740 case... Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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