- 08 Dec, 2011 23 commits
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Santosh Shilimkar authored
CPU local timer(TWD) stops when the CPU is transitioning into deeper C-States. Since these timers are not wakeup capable, we need the wakeup capable global timer to program the wakeup time depending on the next timer expiry. It can be handled by registering a global wakeup capable timer along with local timers marked with (mis)feature flag CLOCK_EVT_FEAT_C3STOP. Then notify the clock events layer from idle code using CLOCK_EVT_NOTIFY_BROADCAST_ENTER/EXIT). ARM local timers are already marked with C3STOP feature. Add the notifiers to OMAP4 CPU idle code for the broadcast entry and exit. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Acked-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Add OMAP4 CPUIDLE support. CPU1 is left with defualt idle and the low power state for it is managed via cpu-hotplug. This patch adds MPUSS low power states in cpuidle. C1 - CPU0 ON + CPU1 ON + MPU ON C2 - CPU0 OFF + CPU1 OFF + MPU CSWR C3 - CPU0 OFF + CPU1 OFF + MPU OSWR OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWr. Ofcourse when MPUSS and CORE PD transitions to OSWR along with device off mode, even the memory contemts are lost which is as good as the PD off state. On OMAP4 because of hardware constraints, no low power states are targeted when both CPUs are online and in SMP mode. The low power states are attempted only when secondary CPU gets offline to OFF through hotplug infrastructure. Thanks to Nicole Chalhoub <n-chalhoub@ti.com> for doing exhaustive C-state latency profiling. Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
On OMAP4 SOC, intecronnects has many write buffers in the async bridges and they need to be drained before CPU enters into standby state. Patch 'OMAP4: PM: Add CPUX OFF mode support' added CPU PM support but OMAP errata i688 (Async Bridge Corruption) needs to be taken care to avoid issues like system freeze, CPU deadlocks, random crashes with register accesses, synchronisation loss on initiators operating on both interconnect port simultaneously. As per the errata, if a data is stalled inside asynchronous bridge because of back pressure, it may be accepted multiple times, creating pointer misalignment that will corrupt next transfers on that data path until next reset of the system (No recovery procedure once the issue is hit, the path remains consistently broken). Async bridge can be found on path between MPU to EMIF and MPU to L3 interconnect. This situation can happen only when the idle is initiated by a Master Request Disconnection (which is trigged by software when executing WFI on CPU). The work-around for this errata needs all the initiators connected through async bridge must ensure that data path is properly drained before issuing WFI. This condition will be met if one Strongly ordered access is performed to the target right before executing the WFI. In MPU case, L3 T2ASYNC FIFO and DDR T2ASYNC FIFO needs to be drained. IO barrier ensure that there is no synchronisation loss on initiators operating on both interconnect port simultaneously. Thanks to Russell for a tip to conver assembly function to C fuction there by reducing 40 odd lines of code from the patch. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
Richard Woodruff <r-woodruff2@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
This patch adds the MPUSS OSWR (Open Switch Retention) support. The MPUSS OSWR configuration is as below. - CPUx L1 and logic lost, MPUSS logic lost, L2 memory is retained OMAP4460 onwards, MPUSS power domain doesn't support OFF state any more anymore just like CORE power domain. The deepest state supported is OSWR. On OMAP4430 secure devices too, MPUSS off mode can't be used because of a bug which alters Ducati and Tesla states. Hence MPUSS off mode as an independent state isn't supported on OMAP44XX devices. Ofcourse when MPUSS power domain transitions to OSWR along with device off mode, it eventually hits off state since memory contents are lost. Hence the MPUSS off mode independent state is not attempted without device off mode. All the necessary infrastructure code for MPUSS off mode is in place as part of this series. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
When MPUSS hits off-mode, L2 cache is lost. This patch adds L2X0 necessary maintenance operations and context restoration in the low power code. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Add WakeupGen and secure GIC low power support to save and restore it's registers. WakeupGen Registers are saved to pre-defined SAR RAM layout and the restore is automatically done by hardware(ROM code) while coming out of MPUSS OSWR or Device off state. Secure GIC is saved using secure API and restored by hardware like WakeupGen. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
With OMAP4 suspend, idle and hotplug series, we no longer need do_wfi() macro. Remove the same. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
This patch adds MPUSS(MPU Sub System) power domain CSWR(Close Switch Retention) support to system wide suspend. For MPUSS power domain to hit retention(CSWR or OSWR), both CPU0 and CPU1 power domains need to be in OFF or DORMANT state, since CPU power domain CSWR is not supported by hardware Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Default arch_idle() isn't good enough for OMAP4 because of aync bridge errata and necessity of NOPs post WFI to avoid speculative prefetch aborts. Hence Use OMAP4 custom omap_do_wfi() hook for default idle. Later in the series, async bridge errata work-around patch updates the omap_do_wfi() with necessary interconnects barriers. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
The SGI(Software Generated Interrupts) are not wakeup capable from low power states. This is known limitation on OMAP4 and needs to be worked around by using software forced clockdomain wake-up. CPU0 forces the CPU1 clockdomain to software force wakeup. More details can be found in OMAP4430 TRM - Version J Section : 4.3.4.2 Power States of CPU0 and CPU1 Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Program non-boot CPUs to hit lowest supported power state when it is off-lined using cpu hotplug framework. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Remove the __INIT from omap_secondary_startup() so that it can be re-used for CPU hotplug. While at this, remove the un-used AUXBOOT register reference. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
This patch adds the CPU0 and CPU1 off mode support. CPUX close switch retention (CSWR) is not supported by hardware design. The CPUx OFF mode isn't supported on OMAP4430 ES1.0 CPUx sleep code is common for hotplug, suspend and CPUilde. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
OMAP WakeupGen is the interrupt controller extension used along with ARM GIC to wake the CPU out from low power states on external interrupts. The WakeupGen unit is responsible for generating the wakeup event from the incoming interrupts and enable bits. It is implemented in the MPU always ON power domain. During normal operation, WakeupGen delivers the external interrupts directly to the GIC. WakeupGen specification has one restriction as per Veyron version 1.6. It is SW responsibility to program interrupt enabling/disabling coherently in the GIC and in the WakeupGen enable registers. That is, a given interrupt for a given CPU is either enable at both GIC and WakeupGen, or disable at both, but no mix. That's the reason the WakeupGen is implemented as an extension of GIC. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Allocate the memory to save secure ram context which needs to be done when MPU is hitting OFF mode. The ROM code expects a physical address to this memory and hence use memblock APIs to reserve this memory as part of .reserve() callback. Maximum size as per secure RAM requirements is allocated. To keep omap1 build working, omap-secure.h file is created under plat-omap directory. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
On OMAP secure/emulation devices, certain APIs are exported by secure code. Add an infrastructure so that relevant operations on secure devices can be implemented using it. While at this, rename omap44xx-smc.S to omap-smc.S since the common APIs can be used on other OMAP's too. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
Initialise hardware supervised mode for all clockdomains if it's supported. Initiate sleep transition for other clockdomains, if they are not being used. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
On OMAP4430 ES1.0, Power Management features are not supported. Avoid omap4_pm_init() on ES1.0 silicon so that we can continue to use same kernel binary to boot on all OMAP4 silicons. The ES1.0 boot failure with OMAP4 PM series was because of the clockdomain initialisation code. Hardware supervised clockdomain mode isn't functional for all clockdomains on OMAP4430 ES1.0 silicon so avoid the same. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Reported-by:
Kevin Hilman <khilman@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
As per OMAP4430 TRM, the dynamic dependency between MPUSS -> EMIF and MPUSS -> L4PER/L3_* and DUCATI -> L3_* clockdomains is enable by default. Refer register CM_MPU_DYNAMICDEP description for details. But these dynamic dependencies doesn't work as expected. The hardware recommendation is to enable static dependencies for above clockdomains. Without this, system locks up or randomly crashes. Signed-off-by:
Rajendra Nayak <rnayak@ti.com> Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Paul Walmsley <paul@pwsan.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
This patch adds SAR RAM support on OMAP4430. SAR RAM used to save and restore the HW context in low power modes. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
This patch exports APIs to get base address for GIC distributor, CPU interface, SCU and PL310 L2 Cache which are used in OMAP4 PM code. This was suggested by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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Santosh Shilimkar authored
OMAP4 L2X0 initialisation code uses BUG_ON() for the ioremap() failure scenarios. Use WARN_ON() instead and allow graceful function exits. This was suggsted by Kevin Hilman <khilman@ti.com> during OMAP4 PM code review. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Kevin Hilman <khilman@ti.com> Tested-by:
Vishwanath BS <vishwanath.bs@ti.com> Signed-off-by:
Kevin Hilman <khilman@ti.com>
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- 06 Dec, 2011 2 commits
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Tony Lindgren authored
ARM restart changes needed changes to common.h to make it local. This conflicted with v3.2-rc4 DSS related hwmod changes that git mergetool was not able to handle. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Tony Lindgren authored
Otherwise we get the following error: In function 'omap_init_consistent_dma_size': error: implicit declaration of function 'init_consistent_dma_size' Signed-off-by:
Tony Lindgren <tony@atomide.com> Acked-by:
Nicolas Pitre <nicolas.pitre@linaro.org> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- 05 Dec, 2011 4 commits
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Russell King authored
Merge branch 'for-rmk' of git://git.kernel.org/pub/scm/linux/kernel/git/will/linux into devel-stable Conflicts: arch/arm/common/gic.c arch/arm/plat-omap/include/plat/common.h
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Santosh Shilimkar authored
Fix the below build break by including common.h arch/arm/mach-omap2/cpuidle34xx.c: In function 'omap3_enter_idle': arch/arm/mach-omap2/cpuidle34xx.c:117: error: implicit declaration of function 'omap_irq_pending' make[1]: *** [arch/arm/mach-omap2/cpuidle34xx.o] Error 1 make: *** [arch/arm/mach-omap2] Error 2 Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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Santosh Shilimkar authored
Fix the build break by adding the necessary irq functions to common header. Signed-off-by:
Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by:
Russell King <rmk+kernel@arm.linux.org.uk>
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- 03 Dec, 2011 1 commit
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Russell King authored
Merge branch 'irqchip-consolidation' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into devel-stable
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- 02 Dec, 2011 8 commits
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Will Deacon authored
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Ming Lei authored
This patch introduces .enable_irq and .disable_irq into struct arm_pmu_platdata, so platform specific irq enablement can be handled after request_irq, and platform specific irq disablement can be handled before free_irq. This patch is for support of pmu irq routed from CTI on omap4. Acked-by:
Jean Pihet <j-pihet@ti.com> Reviewed-by:
Will Deacon <will.deacon@arm.com> Signed-off-by:
Ming Lei <ming.lei@canonical.com> Signed-off-by:
Will Deacon <will.deacon@arm.com>
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Ming Lei authored
OMAP4 uses cross trigger interface(CTI) to route performance monitor irq to GIC, so introduce cti helpers to make access for cti easily. Acked-by:
Jean Pihet <j-pihet@ti.com> Signed-off-by:
Ming Lei <ming.lei@canonical.com> Signed-off-by:
Will Deacon <will.deacon@arm.com>
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Will Deacon authored
armpmu_get_max_events is only called from perf_num_counters, so we can inline it there. It existed as a separate entity as a hangover from the original perf-based oprofile implementation. Signed-off-by:
Will Deacon <will.deacon@arm.com>
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Will Deacon authored
Commit 8f622422 ("perf events: Add generic front-end and back-end stalled cycle event definitions") added two new ABI events for counting stalled cycles. This patch adds support for these new events to the ARM perf implementation. Cc: Jamie Iles <jamie@jamieiles.com> Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by:
Will Deacon <will.deacon@arm.com>
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Will Deacon authored
This patch updates the ARMv7 perf event numbers so that: (1) A consistent naming scheme is used between different CPUs. (2) Only events actually used by Linux are described. (3) Where possible, architected events are used in preference to CPU-specific events. This results in the removal of a load of unused, hardcoded data and makes it more clear as to which events are supported on each PMU. Cc: Jean Pihet <j-pihet@ti.com> Signed-off-by:
Will Deacon <will.deacon@arm.com>
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Axel Lin authored
Trivial fix to fix below build error: CC arch/arm/mach-exynos/mach-universal_c210.o arch/arm/mach-exynos/mach-universal_c210.c:24: error: expected identifier or '(' before '<' token Signed-off-by:
Axel Lin <axel.lin@gmail.com> Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com>
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Axel Lin authored
Fix below build error: CC arch/arm/mach-exynos/cpu.o arch/arm/mach-exynos/cpu.c: In function 'exynos4_init_irq': arch/arm/mach-exynos/cpu.c:245: error: 'gic_bank_offset' undeclared (first use in this function) arch/arm/mach-exynos/cpu.c:245: error: (Each undeclared identifier is reported only once arch/arm/mach-exynos/cpu.c:245: error: for each function it appears in.) arch/arm/mach-exynos/cpu.c:243: warning: unused variable 'bank_offset' make[1]: *** [arch/arm/mach-exynos/cpu.o] Error 1 make: *** [arch/arm/mach-exynos] Error 2 Signed-off-by:
Axel Lin <axel.lin@gmail.com> Signed-off-by:
Marc Zyngier <marc.zyngier@arm.com>
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- 01 Dec, 2011 2 commits
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Linus Torvalds authored
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git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/ocfs2Linus Torvalds authored
* 'upstream-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/ocfs2: (31 commits) ocfs2: avoid unaligned access to dqc_bitmap ocfs2: Use filemap_write_and_wait() instead of write_inode_now() ocfs2: honor O_(D)SYNC flag in fallocate ocfs2: Add a missing journal credit in ocfs2_link_credits() -v2 ocfs2: send correct UUID to cleancache initialization ocfs2: Commit transactions in error cases -v2 ocfs2: make direntry invalid when deleting it fs/ocfs2/dlm/dlmlock.c: free kmem_cache_zalloc'd data using kmem_cache_free ocfs2: Avoid livelock in ocfs2_readpage() ocfs2: serialize unaligned aio ocfs2: Implement llseek() ocfs2: Fix ocfs2_page_mkwrite() ocfs2: Add comment about orphan scanning ocfs2: Clean up messages in the fs ocfs2/cluster: Cluster up now includes network connections too ocfs2/cluster: Add new function o2net_fill_node_map() ocfs2/cluster: Fix output in file elapsed_time_in_ms ocfs2/dlm: dlmlock_remote() needs to account for remastery ocfs2/dlm: Take inflight reference count for remotely mastered resources too ocfs2/dlm: Cleanup dlm_wait_for_node_death() and dlm_wait_for_node_recovery() ...
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