- 24 Mar, 2009 40 commits
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Liu Yu authored
Commit 2a4aca11 removed old method _tlbia(). Signed-off-by:
Liu Yu <yu.liu@freescale.com> Signed-off-by:
Hollis Blanchard <hollisb@us.ibm.com> Signed-off-by:
Avi Kivity <avi@redhat.com>
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Liu Yu authored
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Liu Yu authored
So, KVM needs to read tlbcam_index to know exactly which TLB1 entry is unused by host. Signed-off-by:
Kumar Gala <galak@kernel.crashing.org> Signed-off-by:
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Avi Kivity authored
Two dimensional paging is only confused by it. Signed-off-by: -
Avi Kivity authored
This actually describes what is going on, rather than alerting the reader that something strange is going on. Signed-off-by: -
Marcelo Tosatti authored
Zeroing on mmu_memory_cache_alloc is unnecessary since: - Smaller areas are pre-allocated with kmem_cache_zalloc. - Page pointed by ->spt is overwritten with prefetch_page and entries in page pointed by ->gfns are initialized before reading. [avi: zeroing pages is unnecessary] Signed-off-by:
Marcelo Tosatti <mtosatti@redhat.com> Signed-off-by:
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Joe Perches authored
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Joe Perches <joe@perches.com> Acked-by:
Joerg Roedel <joerg.roedel@amd.com> Signed-off-by:
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Jes Sorensen authored
Provide register layout for struct kvm_regs exposed to userland. Signed-off-by:
Jes Sorensen <jes@sgi.com> Signed-off-by:
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Avi Kivity authored
While the PIT is masked the guest cannot ack the irq, so the reinject logic will never allow the interrupt to be injected. Fix by resetting the reinjection counters on unmask. Unbreaks Xen. Signed-off-by: -
Avi Kivity authored
Allow clients to request notifications when the guest masks or unmasks a particular irq line. This complements irq ack notifications, as the guest will not ack an irq line that is masked. Currently implemented for the ioapic only. Signed-off-by: -
Avi Kivity authored
Two KVM archs support irqchips and two don't. Add a Kconfig item to make selecting between the two models easier. Signed-off-by: -
Avi Kivity authored
Using kvm_mmu_lookup_page() will result in multiple scans of the hash chains; use hlist_for_each_entry_safe() to achieve a single scan instead. Signed-off-by: -
Alexander Graf authored
VMware ESX checks if the microcode level is correct when using a barcelona CPU, in order to see if it actually can use SVM. Let's tell it we're on the safe side... Signed-off-by:
Alexander Graf <agraf@suse.de> Signed-off-by:
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Sheng Yang authored
MSI is always enabled by default for msi2intx=1. But if msi2intx=0, we have to disable MSI if guest require to do so. The patch also discard unnecessary msi2intx judgment if guest want to update MSI state. Notice KVM_DEV_IRQ_ASSIGN_MSI_ACTION is a mask which should cover all MSI related operations, though we only got one for now. Signed-off-by:
Sheng Yang <sheng@linux.intel.com> Signed-off-by:
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Sheng Yang authored
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Hollis Blanchard authored
After the rewrite of KVM's debug support, this code doesn't even build any more. Signed-off-by:
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Avi Kivity authored
Otherwise, two threads can create a PIT in parallel and cause a memory leak. Signed-off-by: -
Avi Kivity authored
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Avi Kivity authored
If we aren't doing mmio there's no need to exit to userspace (which will just be confused). Signed-off-by: -
Avi Kivity authored
Allow emulate_pop() to read into arbitrary memory rather than just the source operand. Needed for complicated instructions like far returns. Signed-off-by: -
Avi Kivity authored
If we've just emulated an instruction, we won't have any valid exit reason and associated information. Fix by moving the clearing of the emulation_required flag to the exit handler. This way the exit handler can notice that we've been emulating and abort early. Signed-off-by: -
Avi Kivity authored
The ususable bit is important for determining state validity; don't clobber it. Signed-off-by: -
Avi Kivity authored
The vmx guest state validity checks are full of bugs. Make them conform to the manual. Signed-off-by: -
Hollis Blanchard authored
e500 has additional interrupt vectors (and corresponding IVORs) for SPE and performance monitoring interrupts. Signed-off-by:
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Hollis Blanchard authored
Although BOOKE_MAX_INTERRUPT has the right value, the meaning is not match. Signed-off-by:
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Hollis Blanchard authored
When itlb or dtlb miss happens, E500 needs to update some mmu registers. So that the auto-load mechanism can work on E500 when write a tlb entry. Signed-off-by:
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Hollis Blanchard authored
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Hollis Blanchard authored
E500 deosn't support this instruction. Signed-off-by:
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Hollis Blanchard authored
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Hollis Blanchard authored
Kernel for E500 need clear dbsr when startup. So add dbsr register in kvm_vcpu_arch for BOOKE. Signed-off-by:
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Hollis Blanchard authored
The Book E code will be shared with e500. I've left PID in kvmppc_core_emulate_op() just so that we don't need to move kvmppc_set_pid() right now. Once we have the e500 implementation, we can probably share that too. Signed-off-by:
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Hollis Blanchard authored
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Hollis Blanchard authored
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Hollis Blanchard authored
e500 will provide its own implementation of these. Signed-off-by:
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Hollis Blanchard authored
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Hollis Blanchard authored
Passing just the TLB index will ease an e500 implementation. Signed-off-by:
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Hollis Blanchard authored
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Hollis Blanchard authored
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Hollis Blanchard authored
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Avi Kivity authored
This is an x86 specific stucture and has no business living in common code. Signed-off-by:
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