- 16 Oct, 2017 1 commit
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Simon Horman authored
Use newly added R-Car GPIO Gen1 fallback compat string in place of now deprecated non-generation specific R-Car GPIO fallback compat string in DT of r8a7778 SoC. As the driver does not match on "renesas,gpio-r8a7778" there are some run-time considerations for this patch: * When a resulting DTB is used with kernels newer than v4.14 this should not have any run-time effect as renesas,rcar-gen1-gpio is matched by the driver since commit dbd1dad2 ("gpio: rcar: add gen[123] fallback compatibility strings") * However, when used with older kernels GPIO will be disabled as no compat string match will be made by the driver. The regression documented above for the new DTB with old kernel case is acceptable in my opinion. Signed-off-by:
Simon Horman <horms+renesas@verge.net.au> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be>
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- 12 Oct, 2017 12 commits
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Jacopo Mondi authored
Enable ostm0 and ostm1 timers to be used as clock source and clockevent source. The timers provides greater accuracy than the already enabled mtu2 one. With these enabled: clocksource: ostm: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 57352151442 ns sched_clock: 32 bits at 33MHz, resolution 30ns, wraps every 64440619504ns ostm: used for clocksource ostm: used for clock events Signed-off-by:
Jacopo Mondi <jacopo+renesas@jmondi.org> Suggested-by:
Chris Brandt <chris.brandt@renesas.com> Reviewed-by:
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Jacopo Mondi authored
Add pin configuration subnode for ETHER pin group. Signed-off-by:
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Biju Das authored
This patch adds DMA properties to the HSUSB node. Signed-off-by:
Biju Das <biju.das@bp.renesas.com> Signed-off-by:
Chris Paterson <chris.paterson2@renesas.com> Reviewed-by:
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Biju Das authored
Signed-off-by:
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Biju Das authored
Enable HS-USB device for the iWave G20D-Q7 carrier board based on RZ/G1M. Also disable the host mode support on usb otg port by default to avoid pin conflicts. Signed-off-by:
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Biju Das authored
Define the R8A7743 generic part of the HS-USB device node. It is up to the board file to enable the device. Signed-off-by:
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Biju Das authored
Signed-off-by:
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Biju Das authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
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Biju Das authored
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by:
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Biju Das authored
Define the r8a7745 generic part of the USB PHY device node. Signed-off-by:
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Biju Das authored
Add device nodes for the r8a7745 internal PCI bridge devices. Signed-off-by:
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Dietmar Eggemann authored
The following 'capacity-dmips-mhz' dt property values are used: Cortex-A15: 1024, Cortex-A7: 539 They have been derived form the cpu_efficiency values: Cortex-A15: 3891, Cortex-A7: 2048 by scaling them so that the Cortex-A15s (big cores) use 1024. The cpu_efficiency values were originally derived from the "Big.LITTLE Processing with ARM Cortex
™ -A15 & Cortex-A7" white paper (http://www.cl.cam.ac.uk/~rdm34/big.LITTLE.pdf). Table 1 lists 1.9x (3891/2048) as the Cortex-A15 vs Cortex-A7 performance ratio for the Dhrystone benchmark. The following platform is affected once cpu-invariant accounting support is re-connected to the task scheduler: r8a7790-lager Signed-off-by:Dietmar Eggemann <dietmar.eggemann@arm.com> Signed-off-by:
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- 09 Oct, 2017 2 commits
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Fabrizio Castro authored
This patch adds a .dtsi that describes the camera daughter board and a .dts to describe the HW made of iWave's RZ/G1M SoM, iWave's RZ/G1M/G1N Qseven carrier board, and the camera daughter board. The camera daughter board .dtsi adds support for ttySC[14]. Signed-off-by:
Fabrizio Castro <fabrizio.castro@bp.renesas.com> Signed-off-by:
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Fabrizio Castro authored
Since the same carrier board may host RZ/G1M and RZ/G1N based Systems on Module, the DT architecture for iwg20d-q7 needs better decoupling. This patch provides: * iwg20d-q7-common.dtsi - its purpose is to define the carrier board definitions, and its content is basically the same as the previous version of r8a7743-iwg20d-q7.dts, only it has no reference to the SoM .dtsi, and that's why the filename doesn't mention the SoC name any more. * r8a7743-iwg20d-q7.dts - its new purpose is to put together the SoM .dtsi (r8a7743-iwg20m.dtsi) and the carrier board .dtsi defined by this very patch, along with "model" and "compatible" properties. The final DT architecture to describe the board is now: r8a7743-iwg20d-q7.dts # Carrier Board + SoM ├── r8a7743-iwg20m.dtsi # SoM │ └── r8a7743.dtsi # SoC └── iwg20d-q7-common.dtsi # Carrier Board and maximizes the reuse of the definitions for the carrier board and for the SoM. Signed-off-by:
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- 06 Oct, 2017 4 commits
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Geert Uytterhoeven authored
Use the preferred generic node name instead of the specific name. Signed-off-by:
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Geert Uytterhoeven authored
Use the preferred generic node name instead of the specific name. Signed-off-by:
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Geert Uytterhoeven authored
Use the preferred generic node name instead of the specific name. Signed-off-by:
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Geert Uytterhoeven authored
Use the preferred generic node name instead of the specific name. Signed-off-by:
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- 05 Oct, 2017 2 commits
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Jacopo Mondi authored
MTU2 multi-function/multi-channel timer/counter is not enabled for GR-Peach board. The timer is used as clock event source to schedule wake-ups, and without this enabled all sleeps not performed through busy waiting hang the board. Signed-off-by:
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Jacopo Mondi authored
Fix 'leds' node name indent as it was wrongly aligned. Signed-off-by:
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- 28 Sep, 2017 2 commits
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Fabrizio Castro authored
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by:
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Fabrizio Castro authored
Add the DT nodes needed by MSIOF[012] interfaces to the SoC dtsi. Also, define aliases for spi[123]. Signed-off-by:
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- 25 Sep, 2017 1 commit
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Fabrizio Castro authored
Enable the SDHI0 controller on iWave RZ/G1E carrier board. Signed-off-by:
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- 21 Sep, 2017 5 commits
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Fabrizio Castro authored
Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by:
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Fabrizio Castro authored
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by:
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Fabrizio Castro authored
Add support for the SPI NOR device used to boot up the system to the System on Module DT. Signed-off-by:
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Fabrizio Castro authored
Add the DT node for the QSPI interface to the SoC dtsi. Signed-off-by:
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Fabrizio Castro authored
Enable the SDHI1 controller on iWave RZ/G1E SoM. Signed-off-by:
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- 19 Sep, 2017 11 commits
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Fabrizio Castro authored
Add the SDHI controllers to the r8a7745 device tree. Signed-off-by:
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Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, but audio is not yet enabled in r8a7792.dtsi, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Geert Uytterhoeven authored
Add properties to describe the reset topology for on-SoC devices: - Add the "#reset-cells" property to the CPG/MSSR device node, - Add resets and reset-names properties to the various device nodes. This allows to reset SoC devices using the Reset Controller API. Note that resets usually match the corresponding module clocks. Exceptions are: - The audio module has resets for the Serial Sound Interfaces only, - The display module has only a single reset for all DU channels, but adding reset properties for the display is postponed. Signed-off-by: -
Biju Das authored
Signed-off-by:
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Wolfram Sang authored
The WP pins are ACTIVE_HIGH, fix it in the DTS. Fixes: 2b41091b ("ARM: dts: alt: add SDHI0 and 1 support") Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
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Biju Das authored
Signed-off-by:
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Biju Das authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
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Biju Das authored
Describe the PCI USB devices that are behind the PCI bridges, adding necessary links to the USB PHY device. Signed-off-by:
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