1. 08 Apr, 2015 3 commits
    • Paolo Bonzini's avatar
      KVM: x86: optimize delivery of TSC deadline timer interrupt · 9c8fd1ba
      Paolo Bonzini authored
      The newly-added tracepoint shows the following results on
      the tscdeadline_latency test:
      
              qemu-kvm-8387  [002]  6425.558974: kvm_vcpu_wakeup:      poll time 10407 ns
              qemu-kvm-8387  [002]  6425.558984: kvm_vcpu_wakeup:      poll time 0 ns
              qemu-kvm-8387  [002]  6425.561242: kvm_vcpu_wakeup:      poll time 10477 ns
              qemu-kvm-8387  [002]  6425.561251: kvm_vcpu_wakeup:      poll time 0 ns
      
      and so on.  This is because we need to go through kvm_vcpu_block again
      after the timer IRQ is injected.  Avoid it by polling once before
      entering kvm_vcpu_block.
      
      On my machine (Xeon E5 Sandy Bridge) this removes about 500 cycles (7%)
      from the latency of the TSC deadline timer.
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      9c8fd1ba
    • Paolo Bonzini's avatar
      KVM: x86: extract blocking logic from __vcpu_run · 362c698f
      Paolo Bonzini authored
      Rename the old __vcpu_run to vcpu_run, and extract part of it to a new
      function vcpu_block.
      
      The next patch will add a new condition in vcpu_block, avoid extra
      indentation.
      Reviewed-by: default avatarDavid Matlack <dmatlack@google.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      362c698f
    • Wanpeng Li's avatar
      kvm: x86: fix x86 eflags fixed bit · 35fd68a3
      Wanpeng Li authored
      Guest can't be booted w/ ept=0, there is a message dumped as below:
      
      If you're running a guest on an Intel machine without unrestricted mode
      support, the failure can be most likely due to the guest entering an invalid
      state for Intel VT. For example, the guest maybe running in big real mode
      which is not supported on less recent Intel processors.
      
      EAX=00000011 EBX=f000d2f6 ECX=00006cac EDX=000f8956
      ESI=bffbdf62 EDI=00000000 EBP=00006c68 ESP=00006c68
      EIP=0000d187 EFL=00000004 [-----P-] CPL=0 II=0 A20=1 SMM=0 HLT=0
      ES =e000 000e0000 ffffffff 00809300 DPL=0 DS16 [-WA]
      CS =f000 000f0000 ffffffff 00809b00 DPL=0 CS16 [-RA]
      SS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
      DS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
      FS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
      GS =0000 00000000 ffffffff 00809300 DPL=0 DS16 [-WA]
      LDT=0000 00000000 0000ffff 00008200 DPL=0 LDT
      TR =0000 00000000 0000ffff 00008b00 DPL=0 TSS32-busy
      GDT=     000f6a80 00000037
      IDT=     000f6abe 00000000
      CR0=00000011 CR2=00000000 CR3=00000000 CR4=00000000
      DR0=0000000000000000 DR1=0000000000000000 DR2=0000000000000000 DR3=0000000000000000
      DR6=00000000ffff0ff0 DR7=0000000000000400
      EFER=0000000000000000
      Code=01 1e b8 6a 2e 0f 01 16 74 6a 0f 20 c0 66 83 c8 01 0f 22 c0 <66> ea 8f d1 0f 00 08 00 b8 10 00 00 00 8e d8 8e c0 8e d0 8e e0 8e e8 89 c8 ff e2 89 c1 b8X
      
      X86 eflags bit 1 is fixed set, which means that 1 << 1 is set instead of 1,
      this patch fix it.
      Signed-off-by: default avatarWanpeng Li <wanpeng.li@linux.intel.com>
      Message-Id: <1428473294-6633-1-git-send-email-wanpeng.li@linux.intel.com>
      Signed-off-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      35fd68a3
  2. 07 Apr, 2015 3 commits
  3. 31 Mar, 2015 9 commits
  4. 30 Mar, 2015 12 commits
  5. 27 Mar, 2015 13 commits
    • James Hogan's avatar
      MIPS: KVM: Wire up MSA capability · d952bd07
      James Hogan authored
      Now that the code is in place for KVM to support MIPS SIMD Architecutre
      (MSA) in MIPS guests, wire up the new KVM_CAP_MIPS_MSA capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of MSA from the guest.
      
      The capability is not supported if the hardware supports MSA vector
      partitioning, since the extra support cannot be tested yet and it
      extends the state that the userland program would have to save.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      d952bd07
    • James Hogan's avatar
      MIPS: KVM: Expose MSA registers · ab86bd60
      James Hogan authored
      Add KVM register numbers for the MIPS SIMD Architecture (MSA) registers,
      and implement access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG
      ioctls when the MSA capability is enabled (exposed in a later patch) and
      present in the guest according to its Config3.MSAP bit.
      
      The MSA vector registers use the same register numbers as the FPU
      registers except with a different size (128bits). Since MSA depends on
      Status.FR=1, these registers are inaccessible when Status.FR=0. These
      registers are returned as a single native endian 128bit value, rather
      than least significant half first with each 64-bit half native endian as
      the kernel uses internally.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      ab86bd60
    • James Hogan's avatar
      MIPS: KVM: Add MSA exception handling · c2537ed9
      James Hogan authored
      Add guest exception handling for MIPS SIMD Architecture (MSA) floating
      point exceptions and MSA disabled exceptions.
      
      MSA floating point exceptions from the guest need passing to the guest
      kernel, so for these a guest MSAFPE is emulated.
      
      MSA disabled exceptions are normally handled by passing a reserved
      instruction exception to the guest (because no guest MSA was supported),
      but the hypervisor can now handle them if the guest has MSA by passing
      an MSA disabled exception to the guest, or if the guest has MSA enabled
      by transparently restoring the guest MSA context and enabling MSA and
      the FPU.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c2537ed9
    • James Hogan's avatar
      MIPS: KVM: Emulate MSA bits in COP0 interface · 2b6009d6
      James Hogan authored
      Emulate MSA related parts of COP0 interface so that the guest will be
      able to enable/disable MSA (Config5.MSAEn) once the MSA capability has
      been wired up.
      
      As with the FPU (Status.CU1) setting Config5.MSAEn has no immediate
      effect if the MSA state isn't live, as MSA state is restored lazily on
      first use. Changes after the MSA state has been restored take immediate
      effect, so that the guest can start getting MSA disabled exceptions
      right away for guest MSA operations. The MSA state is saved lazily too,
      as MSA may get re-enabled in the near future anyway.
      
      A special case is also added for when Status.CU1 is set while FR=0 and
      the MSA state is live. In this case we are at risk of getting reserved
      instruction exceptions if we try and save the MSA state, so we lose the
      MSA state sooner while MSA is still usable.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      2b6009d6
    • James Hogan's avatar
      MIPS: KVM: Add base guest MSA support · 539cb89f
      James Hogan authored
      Add base code for supporting the MIPS SIMD Architecture (MSA) in MIPS
      KVM guests. MSA cannot yet be enabled in the guest, we're just laying
      the groundwork.
      
      As with the FPU, whether the guest's MSA context is loaded is stored in
      another bit in the fpu_inuse vcpu member. This allows MSA to be disabled
      when the guest disables it, but keeping the MSA context loaded so it
      doesn't have to be reloaded if the guest re-enables it.
      
      New assembly code is added for saving and restoring the MSA context,
      restoring only the upper half of the MSA context (for if the FPU context
      is already loaded) and for saving/clearing and restoring MSACSR (which
      can itself cause an MSA FP exception depending on the value). The MSACSR
      is restored before returning to the guest if MSA is already enabled, and
      the existing FP exception die notifier is extended to catch the possible
      MSA FP exception and step over the ctcmsa instruction.
      
      The helper function kvm_own_msa() is added to enable MSA and restore
      the MSA context if it isn't already loaded, which will be used in a
      later patch when the guest attempts to use MSA for the first time and
      triggers an MSA disabled exception.
      
      The existing FPU helpers are extended to handle MSA. kvm_lose_fpu()
      saves the full MSA context if it is loaded (which includes the FPU
      context) and both kvm_lose_fpu() and kvm_drop_fpu() disable MSA.
      
      kvm_own_fpu() also needs to lose any MSA context if FR=0, since there
      would be a risk of getting reserved instruction exceptions if CU1 is
      enabled and we later try and save the MSA context. We shouldn't usually
      hit this case since it will be handled when emulating CU1 changes,
      however there's nothing to stop the guest modifying the Status register
      directly via the comm page, which will cause this case to get hit.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      539cb89f
    • James Hogan's avatar
      MIPS: KVM: Wire up FPU capability · 5fafd874
      James Hogan authored
      Now that the code is in place for KVM to support FPU in MIPS KVM guests,
      wire up the new KVM_CAP_MIPS_FPU capability.
      
      For backwards compatibility, the capability must be explicitly enabled
      in order to detect or make use of the FPU from the guest.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      5fafd874
    • James Hogan's avatar
      MIPS: KVM: Expose FPU registers · 379245cd
      James Hogan authored
      Add KVM register numbers for the MIPS FPU registers, and implement
      access to them with the KVM_GET_ONE_REG / KVM_SET_ONE_REG ioctls when
      the FPU capability is enabled (exposed in a later patch) and present in
      the guest according to its Config1.FP bit.
      
      The registers are accessible in the current mode of the guest, with each
      sized access showing what the guest would see with an equivalent access,
      and like the architecture they may become UNPREDICTABLE if the FR mode
      is changed. When FR=0, odd doubles are inaccessible as they do not exist
      in that mode.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Acked-by: default avatarPaolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: Jonathan Corbet <corbet@lwn.net>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      Cc: linux-api@vger.kernel.org
      Cc: linux-doc@vger.kernel.org
      379245cd
    • James Hogan's avatar
      MIPS: KVM: Add FP exception handling · 1c0cd66a
      James Hogan authored
      Add guest exception handling for floating point exceptions and
      coprocessor 1 unusable exceptions.
      
      Floating point exceptions from the guest need passing to the guest
      kernel, so for these a guest FPE is emulated.
      
      Also, coprocessor 1 unusable exceptions are normally passed straight
      through to the guest (because no guest FPU was supported), but the
      hypervisor can now handle them if the guest has its FPU enabled by
      restoring the guest FPU context and enabling the FPU.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      1c0cd66a
    • James Hogan's avatar
      MIPS: KVM: Emulate FPU bits in COP0 interface · 6cdc65e3
      James Hogan authored
      Emulate FPU related parts of COP0 interface so that the guest will be
      able to enable/disable the following once the FPU capability has been
      wired up:
      - The FPU (Status.CU1)
      - 64-bit FP register mode (Status.FR)
      - Hybrid FP register mode (Config5.FRE)
      
      Changing Status.CU1 has no immediate effect if the FPU state isn't live,
      as the FPU state is restored lazily on first use. After that, changes
      take place immediately in the host Status.CU1, so that the guest can
      start getting coprocessor unusable exceptions right away for guest FPU
      operations if it is disabled. The FPU state is saved lazily too, as the
      FPU may get re-enabled in the near future anyway.
      
      Any change to Status.FR causes the FPU state to be discarded and FPU
      disabled, as the register state is architecturally UNPREDICTABLE after
      such a change. This should also ensure that the FPU state is fully
      initialised (with stale state, but that's fine) when it is next used in
      the new FP mode.
      
      Any change to the Config5.FRE bit is immediately updated in the host
      state so that the guest can get the relevant exceptions right away for
      single-precision FPU operations.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      6cdc65e3
    • James Hogan's avatar
      MIPS: KVM: Add base guest FPU support · 98e91b84
      James Hogan authored
      Add base code for supporting FPU in MIPS KVM guests. The FPU cannot yet
      be enabled in the guest, we're just laying the groundwork.
      
      Whether the guest's FPU context is loaded is stored in a bit in the
      fpu_inuse vcpu member. This allows the FPU to be disabled when the guest
      disables it, but keeping the FPU context loaded so it doesn't have to be
      reloaded if the guest re-enables it.
      
      An fpu_enabled vcpu member stores whether userland has enabled the FPU
      capability (which will be wired up in a later patch).
      
      New assembly code is added for saving and restoring the FPU context, and
      for saving/clearing and restoring FCSR (which can itself cause an FP
      exception depending on the value). The FCSR is restored before returning
      to the guest if the FPU is already enabled, and a die notifier is
      registered to catch the possible FP exception and step over the ctc1
      instruction.
      
      The helper function kvm_lose_fpu() is added to save FPU context and
      disable the FPU, which is used when saving hardware state before a
      context switch or KVM exit (the vcpu_get_regs() callback).
      
      The helper function kvm_own_fpu() is added to enable the FPU and restore
      the FPU context if it isn't already loaded, which will be used in a
      later patch when the guest attempts to use the FPU for the first time
      and triggers a co-processor unusable exception.
      
      The helper function kvm_drop_fpu() is added to discard the FPU context
      and disable the FPU, which will be used in a later patch when the FPU
      state will become architecturally UNPREDICTABLE (change of FR mode) to
      force a reload of [stale] context in the new FR mode.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Paul Burton <paul.burton@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      98e91b84
    • James Hogan's avatar
      MIPS: KVM: Add vcpu_get_regs/vcpu_set_regs callback · b86ecb37
      James Hogan authored
      Add a vcpu_get_regs() and vcpu_set_regs() callbacks for loading and
      restoring context which may be in hardware registers. This may include
      floating point and MIPS SIMD Architecture (MSA) state which may be
      accessed directly by the guest (but restored lazily by the hypervisor),
      and also dedicated guest registers as provided by the VZ ASE.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      b86ecb37
    • James Hogan's avatar
      MIPS: KVM: Add Config4/5 and writing of Config registers · c771607a
      James Hogan authored
      Add Config4 and Config5 co-processor 0 registers, and add capability to
      write the Config1, Config3, Config4, and Config5 registers using the KVM
      API.
      
      Only supported bits can be written, to minimise the chances of the guest
      being given a configuration from e.g. QEMU that is inconsistent with
      that being emulated, and as such the handling is in trap_emul.c as it
      may need to be different for VZ. Currently the only modification
      permitted is to make Config4 and Config5 exist via the M bits, but other
      bits will be added for FPU and MSA support in future patches.
      
      Care should be taken by userland not to change bits without fully
      handling the possible extra state that may then exist and which the
      guest may begin to use and depend on.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      c771607a
    • James Hogan's avatar
      MIPS: KVM: Simplify default guest Config registers · 2211ee81
      James Hogan authored
      Various semi-used definitions exist in kvm_host.h for the default guest
      config registers. Remove them and use the appropriate values directly
      when initialising the Config registers.
      Signed-off-by: default avatarJames Hogan <james.hogan@imgtec.com>
      Cc: Paolo Bonzini <pbonzini@redhat.com>
      Cc: Ralf Baechle <ralf@linux-mips.org>
      Cc: Gleb Natapov <gleb@kernel.org>
      Cc: linux-mips@linux-mips.org
      Cc: kvm@vger.kernel.org
      2211ee81