1. 16 May, 2014 7 commits
  2. 15 May, 2014 8 commits
  3. 14 May, 2014 6 commits
  4. 13 May, 2014 16 commits
  5. 12 May, 2014 3 commits
    • Chon Ming Lee's avatar
      drm/i915/chv: Pipe select change for DP and HDMI · 44f37d1f
      Chon Ming Lee authored
      With additional of pipe C, current 1 bit registers for pipe select
      for HDMI and DP are no longer able to gather for 3 pipes. As a result,
      new bits location in the same registers are added.
      
      For HDMI, VLV uses bit 30, CHV uses bit 24-25.
      
      For DP, VLV uses bit 30, CHV uses bit 16-17.
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      44f37d1f
    • Chon Ming Lee's avatar
      drm/i915/chv: Add phy supports for Cherryview · e4a1d846
      Chon Ming Lee authored
      Added programming phy layer for CHV based on "Application note for 1273
      CHV Display phy".
      
      v2: Rebase the code and do some cleanup.
      v3: Rework based on Ville review.
          -Fix the macro where the ch info need to swap, and add parens to ?
      	 operator.
      	-Fix wrong bit define for DPIO_PCS_SWING_CALC_0 and
      	 DPIO_PCS_SWING_CALC_1 and rename for meaningful.
          -Add some comments for CHV specific DPIO registers.
          -Change the dp margin registery value to decimal to align with the
      	 doc.
      	-Fix the not clearing some value in vlv_dpio_read before write again.
          -Create new hdmi/dp encoder function for chv instead of share with
      	valleyview.
      v4: Rebase the code after rename the DPIO registers define and upstream
      	change.
          Based on Ville review.
          -For unique transition scale selection, after Ville point out, look
      	 like the doc might wrong for the bit 26.  Use bit 27 for ch0 and
      	 ch1.
      	-Break up some dpio write value into two/three steps for readability.
      	-Remove unrelated change.
          -Add some shift define for some registers instead just give the hex
      	value.
          -Fix a bug where write to wrong VLV_TX_DW3.
      v5: Based on Ville review.
      	- Move tx lane latency optimal setting from chv_dp_pre_pll_enable to
      	  chv_pre_enable_dp, and chv_hdmi_pre_pll_enable to
      	  chv_hdmi_pre_enable respectively.
       	- Fix typo in one margin_reg_value for DP_TRAIN_VOLTAGE_SWING_400.
      	- Clear DPIO_TX_UNIQ_TRANS_SCALE_EN for DP and HDMI.
      	- Mask the old deemph and swing bits for hdmi.
      v6: Remove stub for pre_pll_enable for dp and hdmi.
      Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      [vsyrjala: Don't touch panel power sequencing on DP]
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      e4a1d846
    • Chon Ming Lee's avatar
      drm/i915/chv: Add update and enable pll for Cherryview · 9d556c99
      Chon Ming Lee authored
      Added programming PLL for CHV based on "Application note for 1273 CHV
      Display phy".
      
      v2:  -Break the common lane reset into another patch.
           -Break the clock calculation into another patch.
      
          -The changes are based on Ville review.
          -Rework based on DPIO register define naming convention change.
          -Break the dpio write into few lines to improve readability.
          -Correct the udelay during chv_enable_pll.
          -clean up some magic numbers with some new define.
          -program the afc recal bit which was missed.
      
      v3: Based on Ville review
      	-  minor correction of the bit defination
          - add deassert/propagate data lane reset
      
      v4: Corrected the udelay between dclkp enable and pll enable.
      	Minor comment and better way to clear the TX lane reset.
      
      v5: Squash in fixup from Rafael Barbalho.
      
      [vsyrjala: v6: Polish the defines (Imre)]
      Reviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
      Signed-off-by: default avatarChon Ming Lee <chon.ming.lee@intel.com>
      Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
      Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
      9d556c99