- 10 Jan, 2011 40 commits
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Mike Frysinger authored
Encoding the cpu family name apparently confuses people when they try to boot an image on a sub-variant, so encode the specific cpu name and the silicon rev instead. Signed-off-by:Mike Frysinger <vapier@gentoo.org>
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Mike Frysinger authored
When unmasking a GPIO interrupt on a BF54x part, the code will implicitly ack any pending interrupts. This is not what unmasking should do and can cause people to miss interrupts from their devices, so punt the code. Reported-by:
Rutger Hofman <rutger@cs.vu.nl> Signed-off-by:
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Mike Frysinger authored
If there was an error in the lower free functions, we need to pass that back up so the calling process is able to check things. Signed-off-by: -
Mike Frysinger authored
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Andreas Schallenberg authored
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Andreas Schallenberg <Andreas.Schallenberg@3alitydigital.de> Signed-off-by:
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Sonic Zhang authored
On bf518-ezbrd with DSA Ethernet switch enabled, on chip MAC is connecting to phy at address 3. If allowing the netdevice framework to probe both 3 phys of the switch when registering MAC phy, phy at address 1 is checked for link active status other than phy at address 3. If connecting a cable to port 2 and leave port 1 open, link status in phy 2 and 3 are online, while that in phy 1 is offline. So, the phy layer sets wrong offline status to net device on port 3. In this case, no data can be transferred via ethernet port 2. Signed-off-by:
Sonic Zhang <sonic.zhang@analog.com> Signed-off-by:
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Mike Frysinger authored
Common code now invokes the linker directly which causes build failures when using an FDPIC toolchain. So move the emulation setting out of the module-specific LDFLAGS and into the common LDFLAGS. Signed-off-by: -
Vivi Li authored
We check its value at runtime, so we want to avoid garbage across runs. Signed-off-by:
Vivi Li <vivi.li@analog.com> Signed-off-by:
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Sonic Zhang authored
Otherwise, gdb continue operation after a breakpoint is hit may trap into endless breakpoint. Signed-off-by:
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Sonic Zhang authored
When ADEOS and kgdb are both enabled, single step in linux kernel may be scheduled to Xenomai core after return from interrupt handlers. This blocks gdb continue operation after a break point is hit. So, disable interrupt when running gdb single step. Signed-off-by:
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Sonic Zhang authored
When run kgdb testing, it looks like coreb hangs in single step or trap exception without handling anomaly 05000257 properly on bf561 v0.5. But, the anomaly list says it apply to bf561 v0.4 and bellow. Apply its work around to 0.5 temporarily until the behavior and the root cause can be confirmed by the hardware team. Signed-off-by:
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Mike Frysinger authored
The low level assembly needs to use the pseudo_long_call helper so that we use the right call insn when doing kernel XIP. Signed-off-by: -
Sonic Zhang authored
KGDB single step in SMP kernel may hang forever in flushinv without a CSYNC ahead. This is because the core internal write buffers need to be flushed before invalidating the data cache to make sure the insn fetch is not out of sync. Signed-off-by:
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Sonic Zhang authored
The SPORT/UART driver doesn't use the secondary channel pins, so don't try and request them thus keeping other drivers from using them. Signed-off-by:
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Stefan Weil authored
platfrom -> platform This changes a struct name. The related code is conditionally compiled and won't work because the include file linux/gpio-decoder.h is missing, so removing this code would be an even better solution. If the missing include file is added, it must fix the spelling, too. Signed-off-by:
Stefan Weil <weil@mail.berlios.de> Signed-off-by:
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Sonic Zhang authored
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Sonic Zhang authored
When using an uncached DMA region less than 1 MiB, we try to mask off the whole last 1 MiB for it. Unfortunately, this fails as we forgot to subtract one from the calculated mask, leading to the region still be marked as cacheable. Reported-by:
Andrew Rook <andrew.rook@speakerbus.co.uk> Signed-off-by:
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Steven Miao authored
Since linux-2.6.31, the kernel suspend framework will do disable_irq/enable_irq, so save/restore irq in standby and suspend to mem callback should be dropped. Otherwise the common code notices things are enabled and complains. Signed-off-by:
Steven Miao <realmz6@gmail.com> Signed-off-by:
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Michael Hennerich authored
Add more Analog Devices driver entries and refine the differences between Blackfin-specific code and processor independent drivers. Signed-off-by:
Michael Hennerich <michael.hennerich@analog.com> Signed-off-by:
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Mike Frysinger authored
Any consumer of dpmc.h expects to use VR_CTL, so also pull in the new mach/pll.h header for those functions. Signed-off-by: -
Mike Frysinger authored
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Mike Frysinger authored
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Mike Frysinger authored
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Yi Li authored
Currently, sending an interprocessor interrupt (IPI) requires building up a message dynamically which means memory allocation. But often times, we will want to send an IPI in low level contexts where allocation is not possible which may lead to a panic(). So create a per-cpu static array for the message queue and use that instead. Further, while we have two supplemental interrupts, we are currently only using one of them. So use the second one for the most common IPI message of all -- smp_send_reschedule(). This avoids ugly contention for locks which in turn would require an IPI message ... In general, this improves SMP performance, and in some cases allows the SMP port to work in places it wouldn't before. Such as the PREEMPT_RT state where the slab is protected by a per-cpu spin lock. If the slab kmalloc/kfree were to put the task to sleep, and that task was actually the IPI handler, then the system falls down yet again. After running some various stress tests on the system, the static limit of 5 messages seems to work. On the off chance even this overflows, we simply panic(), and we can review that scenario to see if the limit needs to be increased a bit more. Signed-off-by:
Yi Li <yi.li@analog.com> Signed-off-by:
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Graf Yang authored
Since we're breaking apart some inter-header dependencies to avoid more circular loops, move the blackfin_core_id() definition to the func that it is based upon. Signed-off-by:
Graf Yang <graf.yang@analog.com> Signed-off-by:
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Mike Frysinger authored
The SMP code needs "asmlinkage" which linkage.h provides. Signed-off-by: -
Graf Yang authored
Common code expects these to be defined for SMP ports, so add them. Signed-off-by:
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Graf Yang authored
The BF561 mem_map.h header has the __ASSEMBLY__/CONFIG_SMP checks out of order which leads to build errors for assembly code that happens to include this file. Signed-off-by:
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Graf Yang authored
This function takes an irq_handler_t function, but the prototype in the header doesn't match the function definition. This is due to the smp headers needing to avoid circular dependencies. So change the function to take a simple pointer. Signed-off-by:
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Mike Frysinger authored
The common asm-generic non-atomic bitops.h defines test_bit() for us, but we need to use our own version. So redirect the definition of this func to avoid having to inline the rest of the asm-generic file. Signed-off-by: -
Graf Yang authored
The cpu maps are defines provided by common linux/cpumask.h, not local variables. So stop exporting them locally and include the right header for their definition. Signed-off-by:
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Graf Yang authored
The external functions are named __raw_xxx, not arch_xxx, so rename the prototypes to match reality. This fixes some simple build errors in the bfin_ksyms.c code which exports these helpers to modules. Signed-off-by:
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Sonic Zhang authored
Rather than maintain Kconfig entries where people have to enter raw numbers and hardcode lists of addresses/pins in the driver itself, push it all to platform resources. This lets us simplify the driver, the Kconfig, and gives board porters greater flexibility. In the process, we need to also start supporting the early platform interface. Not a big deal, but it causes the patch to be bigger than a simple resource relocation. All the Blackfin boards already have their resources updated and in place for this change. Signed-off-by:
Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by:
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Mike Frysinger authored
Looks like I missed a few new spots when renaming the SICA macros. Signed-off-by: -
Mike Frysinger authored
These were only included because of the irq handling of the PLL funcs, and those PLL funcs have been moved out into their own header now. Signed-off-by: -
Mike Frysinger authored
The defBF512.h header exists only to include defBF51x_base.h, and it is the only place where defBF51x_base.h is included. So move the contents of the defBF51x_base.h header into the defBF512.h header. Same situation for the other def/cdef pairs. Signed-off-by: -
Mike Frysinger authored
The main asm/blackfin.h header will pull in mach/blackfin.h to get all the fun Blackfin defines. So having any of the sub-mach headers trying to include asm/blackfin.h makes no sense -- punt it. The mach/blackfin.h header takes care of including the part-specific def headers which in turn will include any other needed def file. Similarly, it takes care of pulling in the part-specific cdef header. So move this logic out of the blackfin.h when necessary. Further, make sure the cdef headers do not waste time including the def headers again. Since all parts need the common def/cdef headers, move this logic out of the part-specific headers and into the mach/blackfin.h file. Finally, we need to split the BF539 def header since the BF538 does not have MXVR and we don't want to expose those MMRs. So now all parts should have the same behavior: mach/blackfin.h asm/def_LPBlackfin.h part-specific def.h if ! asm asm/cdef_LPBlackfin.h part-specific cdef.h And the sub def/cdef headers only tail into what they need. Signed-off-by: -
Mike Frysinger authored
We don't want the BF533 to be different in terms of its MMR headers, so merge the FIO_FLAG helpers back into the normal place. To avoid circular dependencies with headers, turn the inline C funcs into CPP defines. Not like there will be any code size differences. Signed-off-by: -
Mike Frysinger authored
Since the SMP code paths tend to compile fail a lot, start a SMP defconfig so our nightly build tools will automatically test it. Signed-off-by: -
Mike Frysinger authored
We don't want people banging on MMRs directly. As for the ip0x board, it shouldn't need to muck with the CS pin directly as the Blackfin SPI bus master driver takes care of driving this. Signed-off-by:
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