1. 12 Apr, 2017 15 commits
  2. 04 Apr, 2017 3 commits
  3. 30 Mar, 2017 4 commits
    • Geert Uytterhoeven's avatar
      clk: renesas: rcar-gen3-cpg: Add support for RCLK on R-Car H3 ES2.0 · bb195306
      Geert Uytterhoeven authored
      Starting with R-Car H3 ES2.0, the parent of RCLK is selected using MD28.
      
      Add support for that, but retain the old behavior for R-Car H3 ES1.x and
      M3-W ES1.0 using a quirk.
      
      Inspired by a patch by Takeshi Kihara in the BSP.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      Cc: Takeshi Kihara <takeshi.kihara.df@renesas.com>
      bb195306
    • Geert Uytterhoeven's avatar
      clk: renesas: r8a7795: Add support for R-Car H3 ES2.0 · 5573d194
      Geert Uytterhoeven authored
      The Clock Pulse Generator / Module Standby and Software Reset module in
      R-Car H3 ES2.0 differs from ES1.x in the following areas:
        - More core clocks (S0D2, S0D3, S0D6, S0D8, S0D12),
        - Different parent clocks for AUDMAC, EtherAVB, FCP, FDP, IMR,
          SYS-DMAC, VIN, VSPB, VSPI,
        - Removal of modules CSI21, FCPCI, FCPF2, FCPVD3, FCPVI2, FDP1-2,
          USB3-IF1, VSPD3, VSPI2,
        - Addition of modules EHCI3, HS-USB-IF3, USB-DMAC3-0, USB-DMAC3-1.
      
      The goal is twofold:
        1. Support both the ES1.x and ES2.0 SoC revisions in a single binary
           for now,
        2. Make it clear which code supports ES1.x, so it can easily be
           identified and removed later, when production SoCs are deemed
           ubiquitous.
      
      This is achieved by:
        - Updating the clock tables for the latest revision (ES2.0), but not
          removing clocks that only exist on earlier revisions (ES1.x),
        - Detecting the SoC revision at runtime using the new soc_device_match()
          API, and fixing up the clocks tables to match the actual SoC
          revision, by:
            - NULLifying core and module clocks of modules that do not exist,
            - Reparenting module clocks that have a different parent on ES1.x.
      
      Based on R-Car Gen3 Hardware User's Manual rev. 0.53E.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      5573d194
    • Geert Uytterhoeven's avatar
      clk: renesas: Add r8a7795 ES2.0 CPG Core Clock Definitions · 89f1b1c6
      Geert Uytterhoeven authored
      Add all R-Car H3 ES2.0 Clock Pulse Generator Core Clock Outputs, as
      listed in Table 8.2a ("List of Clocks [R-Car H3]") of the R-Car Gen3
      Hardware User's Manual rev. 0.53E.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      89f1b1c6
    • Geert Uytterhoeven's avatar
      clk: renesas: cpg-mssr: Add support for fixing up clock tables · 48d0341e
      Geert Uytterhoeven authored
      The same SoC may have different clocks and/or module clock parents,
      depending on SoC revision.  One option is to use different sets of clock
      tables for each SoC revision.  However, if the differences are small, it
      is much more space-efficient to have a single set of clock tables, and
      fix those up at runtime instead.
      
      Hence provide three helpers:
        - Two helpers to NULLify core and module clocks that do not exist on
          some revisions (NULLified clocks are skipped during the registration
          phase),
        - One helper to reparent module clocks that have different clock
          parents.
      Signed-off-by: default avatarGeert Uytterhoeven <geert+renesas@glider.be>
      48d0341e
  4. 23 Mar, 2017 1 commit
  5. 22 Mar, 2017 3 commits
  6. 21 Mar, 2017 7 commits
  7. 20 Mar, 2017 7 commits