Signed-off-by: David S. Miller <davem@davemloft.net>

up->irq was just duplicating up->port.irq so
delete the former and only use the latter.  We
were not initializing up->port.irq so this would
cause port shutdown crashes when synchronize_irq()
was called.

Based upon a bug report and patch from
RChan <rspchan@starhub.net.sg>
Signed-off-by: David S. Miller <davem@davemloft.net>

Signed-off-by: David S. Miller <davem@davemloft.net>

Just like on x86
Signed-off-by: David S. Miller <davem@davemloft.net>

m68k used to do this by hand, but it really ends up being needed
for any environment that does cross-builds, so just do it
unconditionally.

This should mean that you never need to cross-build sparse or
have any other hacks for checking a cross-built environment.

This way you can do a checking run on UP too - even if the
locks don't actually _matter_, they should still be right,
I'd hope.

In particular, a function that is called with a lock held, and
releases it only to re-acquire it needs to be annotated as such,
since otherwise sparse will complain about an unexpected unlock,
even though "globally" the lock is constant over the call.

This annotates the scheduler routines for locking, telling
what locks a function releases or acquires, allowing sparse
to check the lock usage (and documenting it at the same time).

and atomic_dec_and_lock.

This means that we now have all of the spinlock context counting
infrastructure in place, and you can check-compile the kernel with 
sparse -Wcontext.

We rename the actual architecture-specific low-level implementation
to have a prepended underscore: "_atomic_dec_and_lock()".

This extra macro indirection is so that we can make the macro do
the lock context counting. That will be the next patch.

into ppc970.osdl.org:/home/torvalds/v2.6/linux

- Add definition for SActive register
- Add most interrupt sources to default interrupt mask
- Write low 32 bits of FIS address to PxFB, where they belong
- Set command active bit in PxSACT before setting command issue bit in PxCI
- Announce Sub Class Code in driver info message [IDE, SATA or RAID]

and additionally, from me [jgarzik]:
- ignore ports-implemented bitmap for now; it's a write-only register
  that silly BIOSen initialize incorreclty
Signed-off-by: Matthijs Melchior <mmelchior@xs4all.nl>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

into ppc970.osdl.org:/home/torvalds/v2.6/linux

That's "cpu", not "cpy".

 - Add the PARISC tag (Thibaut Varene)
 - Mark some existing PA-RISC specific entries with it (Thibaut Varene)
 - Document pdcchassis (Thibaut Varene)

 - Fix "sti= parameter ignored by stifb" bug (Stuart Brady)
 - Fix the STI crash with HCRX-24 in 32bpp mode (Helge Deller)

100% cosmetic:  rename various symbols with 'sata' in them to 'ata',
in preparation for addition of support for a PATA controller.
Signed-off-by: Tobias Lorenz <tobias.lorenz@gmx.net>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

Description: Uses msleep() / ssleep() [as appropriate] instead of
schedule_timeout() to guarantee the task delays as expected.
Signed-off-by: Nishanth Aravamudan <nacc@us.ibm.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Fix __init section usage:
rhine_resume calls enable_mmio, so latter cannot be __devinit;
Error: ./drivers/net/via-rhine.o .text refers to 0000000000000925 R_X86_64_PC32
.init.text+0xfffffffffffffffc
Signed-off-by: Randy Dunlap <rddunlap@osdl.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

This patch adds a few memory barriers, cleans up a little bit the
use of the "status" field in the rx & tx routines, and adds probing
for the external PHY to the driver.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

This patch does an indentation fix to amd8111e_rx_poll() which was
incorrectly shifting left in the middle of a while() loop, thus
rendering the function difficult to read. There is no actual code
change.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

My intel.com address will bounce.
Signed-off-by: Scott Feldman <sfeldma@pobox.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

It looks like this bit got mismerged (pci.h removed but DMA arguments
convertion missing).
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

ARM udelay can't cope with >2ms delays.
Signed-off-by: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>

into pobox.com:/garz/repo/libata-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux

Since bit 0 is only set when the MM is mapped onto the CPU, we can use
this rather than comparing the MM pointer with current->active_mm.
This simplifies the inline cache flushing and tlb code.