- 14 Jan, 2019 40 commits
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Derek Lai authored
[Why] If eDP ver >= 1.4, the Source device must use LINK_RATE_SET. [How] Get LINK_RATE_SET by reading DPCD 10h-1fh, then write DPCD 00115h before link training. Signed-off-by:
Derek Lai <Derek.Lai@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Joshua Aberback authored
[Why] In certain scenarios the ramp parameter come in as NULL, which crashes because this function doesn't guard properly in the early return. [How] - parameter mapUserRamp should be the guard (false means no ramp) - remove checking ramp in early return Signed-off-by:
Joshua Aberback <joshua.aberback@amd.com> Reviewed-by:
Sivapiriyan Kumarasamy <Sivapiriyan.Kumarasamy@amd.com> Acked-by:
Eryk Brol <Eryk.Brol@amd.com> Acked-by:
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Martin Tsai authored
[why] To resume system before entering S0i3 completely will cause PSP not reload DMCU FW since there is not HW power state change. In this case, driver cannot get correct DMCU version from IRAM since driver override it and DMCU didn't reload to update it. It makes driver return false in dcn10_dmcu_init(). [how] 1.To redefine DMCU_SCRATCH to identify different DMCU state. 2.To reserve IRAM 0xF0~0xFF write by DMCU only. 3.To remove dcn10_get_dmcu_state Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Charlene Liu authored
[Why] PPLIB not receive the PME when unplug. Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Tony Cheng authored
[why] separate register access from logic to allow us abstract register sequences [how] consolidate mask and value first then apply to register. Signed-off-by:
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Leo Li authored
This reverts commit 717276b9. The reverted patch was a workaround that addressed an issue fixed by: 4364bcb2 ("drm: Get ref on CRTC commit object when waiting for flip_done") Signed-off-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Signed-off-by:
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abdoulaye berthe authored
[Why] 1-Test equipment does not reset test automation flag after completing current test causing the next test to fail. 2.When test request is empty, we shouldn't ack the test. [How] 1-Driver should always clear test equipment automation test request when request is completed. 2-Driver should clear test equipement test automation if driver does not complete the request. Signed-off-by:
abdoulaye berthe <abdoulaye.berthe@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Josip Pavic authored
[Why] When the DMCU's iRAM definition was moved to the newly created power_helpers, a #pragma pack was lost, causing the iRAM to be misaligned [How] Restore the #pragma pack Signed-off-by:
Josip Pavic <Josip.Pavic@amd.com> Reviewed-by:
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Joshua Aberback authored
[Why] The driver will crash on dce hardware due to a null function pointer. [How] - bring back "program_csc_matrix" functionality as "program_output_csc" for dce110 - dce110 doesn't use the "opp_id" parameter, so use 0 when there's no hubp Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Steven Chiu authored
Signed-off-by:
Steven Chiu <steven.chiu@amd.com> Reviewed-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Nicholas Kazlauskas authored
[Why] This fixes a stuttering issue that occurs when moving a hardware cursor when VRR is enabled. Previously when VRR is enabled atomic check will grab the connector state for every atomic update. This has to lock the connector in order to do so. The locking is bad enough by itself for performance, but it gets worse with what we do just below that - add all the planes for the CRTC to the commit. This prevents the cursor fast path from working - there's more than one plane now. With state->allow_modeset = true on top of this, it also adds and removes all the planes from the DC context triggering a full (very slow) update in DC. [How] We need the connector state to get the VRR min/max capbilities, but we only need them when there's a CRTC mode change or when VRR is toggled. The condition has been updated accordingly. Fixes: 3cc22f281318 ("drm/amdgpu: Set FreeSync state using drm VRR properties") Signed-off-by: -
Kenneth Feng authored
acg btc was added to Vega12 Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Felix Kuehling authored
dGPUs need their own topology devices. Don't assign them to APU topology devices with CPU cores. Bug: https://github.com/RadeonOpenCompute/ROCK-Kernel-Driver/issues/66Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Tested-by:
Elias Konstantinidis <ekondis@gmail.com> Acked-by:
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Felix Kuehling authored
ifdef x86_64 specific code. Allow enabling CONFIG_HSA_AMD on ARM64. v2: Fixed a compiler warning due to an unused variable CC: Mark Nutter <Mark.Nutter@arm.com> Signed-off-by:
Mark Nutter <Mark.Nutter@arm.com> Acked-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Alex Deucher authored
To deal with situations like kexec or GPU VM passthrough where the device may have been used previously without a proper GPU reset between. v2: rebase bug: https://bugs.freedesktop.org/show_bug.cgi?id=108585 bug: https://bugs.freedesktop.org/show_bug.cgi?id=108754Reviewed-by:
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Alex Deucher authored
SOC15 chips require a reset if the driver was previously loaded because the PSP can only be loaded once between each reset. v2: rebase, handle multiple asic funcs Reviewed-by:
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Alex Deucher authored
VI chips require a reset if the driver was previously loaded because the SMU can only be loaded once between each reset. v2: rebase Reviewed-by:
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Alex Deucher authored
CIK chips require a reset if the driver was previously loaded because the SMU can only be loaded once between each reset. v2: rebase Reviewed-by:
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Alex Deucher authored
SI chips don't require a reset on reload due to the nature of the SMU on them. v2: rebase Reviewed-by:
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Alex Deucher authored
Used to determine if we need to reset the asic on init due to the driver having been previously loaded or not shutdown cleanly. E.g., kexec or VM passthrough. v2: rebase Reviewed-by:
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Alex Deucher authored
Expose sclk (gfx clock) and mclk (memory clock) via hwmon compatible interface. hwmon does not actually formally specify a frequency type attribute, but these are compatible with the format of the other attributes exposed via hwmon. Units are hertz. freq1_input - GPU gfx/compute clock in hertz freq2_input - GPU memory clock in hertz (dGPU only) Reviewed-by:
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Kent Russell authored
Add a sysfs file that reports the number of bytes transmitted and received in the last second. This can be used to approximate the PCIe bandwidth usage over the last second. v2: Clarify use of mps as estimation of bandwidth v3: Don't make the file on APUs v4: Early exit for APUs in the read function, change output to display "packets-received packets-sent mps" v5: fix missing header for si (Alex) Signed-off-by:Kent Russell <kent.russell@amd.com> Reviewed-by:
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Kent Russell authored
We need these offsets for PCIE perf counters, so include them as well as the the previously-used defines from the nbio_*.c files v2: Return NBIF definitions back to previous files Signed-off-by:
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Tom St Denis authored
v2: Move locks around in other functions so that this function can stand on its own. Also only hold the hive specific lock for add/remove device instead of the driver global lock so you can't add/remove devices in parallel from one hive. v3: add reset_lock Acked-by: Shaoyun.liu < Shaoyun.liu@amd.com> Signed-off-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Leo Li authored
[Why] To reduce indent in dm_update_crtcs, and to make it operate on single instances. [How] Move iteration of plane states into atomic_check. No functional change is intended. Signed-off-by:
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Leo Li authored
[Why] To reduce indentation of dm_update_planes, and to make it operate on single plane instances. [How] Move iteration of plane states into atomic_check. No functional change is intended. Signed-off-by:
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shaoyunl authored
Add message print out and return -EINVAL when driver can not get valid hive from hive arrary on xgmi configuration Signed-off-by:
shaoyunl <shaoyun.liu@amd.com> Reviewed-by:
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Hawking Zhang authored
get_fw_type and prep_cmd_buf should be common interface instead of IP specific ones Signed-off-by:
Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by:
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Hawking Zhang authored
GFX_FW_TYPE_RLC_RESTORE_LIST_CNTL was renamed to GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL in latest psp_gfx_if drop Signed-off-by:
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Gustavo A. R. Silva authored
Fix boolean expressions by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 9a4b7d4c ("drm/amdgpu: Add vm context module param") Reviewed-by:
Gustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by:
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Emily Deng authored
When init fail, send rel init, req_fini and rel_fini to host for the finishing routine. Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Gustavo A. R. Silva authored
Fix boolean expression by using logical AND operator '&&' instead of bitwise operator '&'. This issue was detected with the help of Coccinelle. Fixes: 6d04ee9d ("drm/amd/display: Restructuring and cleaning up DML") Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Christian König authored
Note if this is a retry fault or not and cleanup the message a bit. Signed-off-by:
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wentalou authored
distinguish ip_reinit_early_sriov and ip_reinit_late_sriov by different log RE-INIT-early and RE-INIT-late Signed-off-by:
Wentao Lou <Wentao.Lou@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] Hardware support for Delta Color Compression (DCC) decompression is available in DC for GFX9 but there's no way for userspace to enable the feature. Enabling the feature can provide improved GFX performance and power savings in many situations. [How] The GFX9 DCC parameters are passed to amdgpu_dm from AMDGPU via the amdgpu_bo tiling_flags. The plane capability is queried and the parameters are set accordingly. The DCC address is given via a 256 byte aligned offset on the framebuffer address. The DCC address is updated whenever the buffer address changes. Signed-off-by:
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Christian König authored
To distinct on which IH ring an IV was found. Signed-off-by:
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Christian König authored
When an ring buffer overflow happens the appropriate bit is set in the WPTR register which is also written back to memory. But clearing the bit in the WPTR doesn't trigger another memory writeback. So what can happen is that we end up processing the buffer overflow over and over again because the bit is never cleared. Resulting in a random system lockup because of an infinite loop in an interrupt handler. This is 100% reproducible on Vega10, but it's most likely an issue we have in the driver over all generations all the way back to radeon. v2: rebase Signed-off-by:
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Christian König authored
Calculate all the addresses and pointers in amdgpu_ih.c Signed-off-by:
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Christian König authored
Let's start to support multiple rings. v2: decode IV is needed as well Signed-off-by:
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Prike Liang authored
As the PG was setted by each IP block durinng IP early init thus remove the unused phm_enable_clock_power_gatings related funcs. Signed-off-by:
Prike Liang <Prike.Liang@amd.com> Reviewed-by:
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