- 13 Jan, 2010 2 commits
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Alex Deucher authored
Unhandled vectors can be safely ignored, no need to spam the kernel log by default. Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
Based on radeonfb code and recent ddx fix. v2: minor formatting fix from Michel Dänzer Signed-off-by:
Michel Dänzer <michel@daenzer.net> Tested-by:
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- 11 Jan, 2010 1 commit
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Alex Deucher authored
- r4xx/rs6xx: add support for extended pixel shader instruction/temp regs - r5xx: add SM3 regs Signed-off-by:
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- 08 Jan, 2010 13 commits
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Jerome Glisse authored
If for any reason we haven't installed handler we shouldn't try to enable IRQ/MSI on the hw so we don't get unhandled IRQ/MSI which makes the kernel sad. Signed-off-by:
Jerome Glisse <jglisse@redhat.com> Signed-off-by:
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Jerome Glisse authored
In some case vblank might not be initialized and we shouldn't try to use associated function. This patch make sure this is the case. It also export drm_vblank_cleanup so driver can cleanup vblank if for any reason IRQ/MSI is not working. Signed-off-by:
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Alexander Beregalov authored
Signed-off-by:
Alexander Beregalov <a.beregalov@gmail.com> Signed-off-by:
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Jerome Glisse authored
In some case we weren't releasing the AGP device at module unloading. This leaded to unfunctional AGP at next module load. This patch make sure we release the AGP bus if we acquire it. Signed-off-by:
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Jerome Glisse authored
R300 family will hard lockup if host path read cache flush is done through MMIO to HOST_PATH_CNTL. But scheduling same flush through ring seems harmless. This patch remove the hdp_flush callback and add a flush after each fence emission which means a flush after each IB schedule. Thus we should have same behavior without the hard lockup. Tested on R100,R200,R300,R400,R500,R600,R700 family. V2: Adjust fence counts in r600_blit_prepare_copy() Signed-off-by:
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Corbin Simpson authored
Long story short, this fixes sporadic hardlocks with my rv410 during times of intense 2D acceleration (Flash on Fx3). V2: Fix indentation and move errata_fini to suspend function so we don't leak scratch register over suspend/resume cycle. V3: Move scratch_reg to asic specific structure (aim is to slowly move stuff to asic specific structure and avoid poluting radeon_device struct with asic specific variables) Signed-off-by:Corbin Simpson <MostAwesomeDude@gmail.com> Signed-off-by:
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Alex Deucher authored
This detects if the sideport memory is enabled and if it is VRAM is evicted on suspend/resume. This should fix s/r issues on some IGPs. Signed-off-by:
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Darren Jenkins authored
There are a couple of array overruns, and some associated confusion in the code. This is just a wild guess at what the code should actually look like. Coverity CID: 13305 13306 agd5f: fix up the original intent of the timing code Signed-off-by:
Darren Jenkins <darrenrjenkins@gmail.com> Signed-off-by:
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Alex Deucher authored
This is displayport used for internal connections such as laptop panels and systems with integrated monitors. Signed-off-by:
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Alex Deucher authored
Add a new connector type for eDP (embedded displayport) eDP is more or less the same as DP but there are some cases when you might want to handle it separately. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
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Alex Deucher authored
Makes it easier to keep in sync with ddx and the upstream AMD versions. Signed-off-by:
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Alex Deucher authored
Also remove the problematic enums that were unused remnants from the ddx. Signed-off-by:
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- 07 Jan, 2010 6 commits
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Luca Tettamanti authored
The mask happens to be the same, but the IH is reading the status, not the not the control register. Signed-off-by:
Luca Tettamanti <kronos.it@gmail.com> Signed-off-by:
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Darren Jenkins authored
If a NULL value is possible, the dereference should only occur after the NULL test. Coverity CID: 13338 Signed-off-by:
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Darren Jenkins authored
If a NULL value is possible, the dereference should only occur after the NULL test. Coverity CID: 13335 Signed-off-by:
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Darren Jenkins authored
If a NULL value is possible, the dereference should only occur after the NULL test. Coverity CID: 13334 Signed-off-by:
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Darren Jenkins authored
The encoder variable can be NULL in this function so I believe it should be checked before dereference. Coverity CID: 13253 [airlied: extremely unlikely to happen] Signed-off-by:
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Jiri Slaby authored
Stanse found a memory leak in radeon_master_create. master_priv is not freed/assigned on all paths. Fix that. Signed-off-by:
Jiri Slaby <jslaby@suse.cz> Signed-off-by:
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- 06 Jan, 2010 3 commits
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Alex Deucher authored
Should fix fdo bug 25741 Signed-off-by:
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Alex Deucher authored
Look up primary dac adj values from the table if there is no bios or bios dac table to reference. The lookup table may need to be adjusted for certain families. Should fix kernel bug 14945. Signed-off-by:
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Alex Deucher authored
if necessary for combios Some early combios radeon cards don't have a connector table or dac table in the bios, if they do not, fallback to the default tables. Should fix kernel bug 14963. Signed-off-by:
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- 23 Dec, 2009 15 commits
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Alex Deucher authored
[airlied: just adding this for completeness to avoid drift between public atombios.h files] Signed-off-by:
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Alex Deucher authored
When linking multiple encoders to a connector, make sure to not link LVDS with another connector. Some bioses have the same i2c line for LVDS and VGA. Signed-off-by:
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Jerome Glisse authored
This patch add a function which check module argument to be valid. On invalid argument it prints a warning and setback the default value. V2: Allow 0 for vram limit & agp mode which are the default value Signed-off-by:
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Jerome Glisse authored
Add boolean to record if some part of the driver are initialized or not this allow to avoid a crash when trying to cleanup uninitialized structure members. Signed-off-by:
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Alex Deucher authored
This fixes LVDS on some mac laptops without a panel edid. v2 - Set proper mode type flags v3 - Note that this is not neceesarily the exact panel mode, but an approximation based on the cvt formula. For these systems we should ideally read the mode info out of the registers or add a mode table, but this works and is much simpler. v4 - Update comments and debug message. Signed-off-by:
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Marek Olšák authored
There are 2 formats: ATI1N: 64 bits per 4x4 block, one-channel format ATI2N: 128 bits per 4x4 block, two-channel format Signed-off-by: -
Marek Olšák authored
Because hardware cannot disable all colorbuffers directly to do depth-only rendering, a user should: - disable reading from a colorbuffer in blending - disable fastfill - set the color channel mask to 0 to prevent writing to a colorbuffer Signed-off-by: -
Rafał Miłecki authored
V2: detect IGP cards (which don't have own memory) Signed-off-by:
Rafał Miłecki <zajec5@gmail.com> Acked-by:
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Rafał Miłecki authored
This just adds a mutex around the atombios table execution so we don't call it from two contexts at once. Signed-off-by:
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Alex Deucher authored
we were just using 1 before. reported on irc by soreau Signed-off-by:
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Alex Deucher authored
This makes 640x480 on my R100 work again, both in aspect and centered mode. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
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Marin Mitov authored
warning: 'width' may be used uninitialized in this function drivers/gpu/drm/drm_edid.c Signed-off-by:
Marin Mitov <mitov@issp.bas.bg> Signed-off-by:
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Bob Gleitsmann authored
This is from bug 25728. [airlied: I'm just forwarding the patch for review, Thomas, ickle?] Acked-by:
Thomas Hellstrom <thellstrom@vmware.com> Signed-off-by:
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Thomas Hellstrom authored
Improve the command verifier to catch all occurences of surface handles, and translate to SIDs. This way DMA buffers and 3D surfaces share a common handle space, which makes it possible for the kms code to differentiate. Signed-off-by:
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