- 26 Sep, 2017 40 commits
-
-
Charlene Liu authored
Signed-off-by:
Charlene Liu <charlene.liu@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Harry Wentland <Harry.Wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
-
Roman Li authored
1.Fixing error message: "wait counter exceeded, changes to HW not applied" 2. Added "FBC status changed to 0/1" logs Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
-
Harry Wentland authored
Signed-off-by:
-
Leo (Sunpeng) Li authored
Previously atomic_check assumed that dc_state is allocated and filled in. This is not the case when we hit EDEADLK and have to backup and retry. We could change atomic_state_clear but that revealed some other problems. For now let's create and construct dc_state in atomic_check. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
-
Leo (Sunpeng) Li authored
For less repetition and easy debugging. Signed-off-by:
-
Andrey Grodzovsky authored
Until now new context would start as empty, then populated with exsisting pipes + new. Now we start with duplication of existing context and then add/delete from the context pipes as needed. This allows to do a per stream resource population, start discarding dc_validation_set and by this brings DC closer to to DRM. v2: Add some fixes and rebase. Signed-off-by:
Andrey Grodzovsky <Andrey.Grodzovsky@amd.com> Reviewed-by:
-
Tony Cheng authored
new per SoC interface instead legacy interface with lots of un-used field that only cause confusion model pp_smu like one of our HW objects with func_ptr interface to call into it. struct pp_smu as handle to call pp/smu Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
-
Zeyu Fan authored
Signed-off-by:
Zeyu Fan <Zeyu.Fan@amd.com> Reviewed-by:
-
Yue Hin Lau authored
Signed-off-by:
Yue Hin Lau <Yuehin.Lau@amd.com> Reviewed-by:
-
Tony Cheng authored
Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
-
Roman Li authored
- Fixing compilation with ENABLE_FBC flag which was broken after flattening core_dc to dc Signed-off-by:
Jerry Zuo <Jerry.Zuo@amd.com> Acked-by:
-
Harry Wentland authored
See https://lists.freedesktop.org/archives/dri-devel/2017-August/149938.htmlSigned-off-by:
Jordan Lazare <Jordan.Lazare@amd.com> Acked-by:
-
Charlene Liu authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
-
Yongqiang Sun authored
Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
-
Bhawanpreet Lakha authored
-Flattening core_dc to dc Signed-off-by:
-
Dmytro Laktyushkin authored
Signed-off-by:
-
Charlene Liu authored
also pass-in correct dispclk tor DMCU Signed-off-by:
-
Bhawanpreet Lakha authored
-Change dcn_ip into pointer -Change dcn_soc into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by:
-
Corbin McElhanney authored
This comment explains a previous change that adds some complexity to the context free in dc: commit 9ad58779a895 ("drm/amd/display: Fix accessing freed memory") Signed-off-by:Corbin McElhanney <corbin.mcelhanney@amd.com> Reviewed-by:
-
Bhawanpreet Lakha authored
-Change bw_calcs_dceip into pointer -Change bw_calcs_vbios into pointer This is needed for flattening of core_dc into dc, as without this the diags build fails Signed-off-by:
-
Duke Du authored
Signed-off-by:
Duke Du <Duke.Du@amd.com> Reviewed-by:
-
Jerry Zuo authored
Current ref_count inc/dec is not guarded by locks which leads to a raced condition where two threads try to access the variable at the same time. In this case, both might act on the same cached value and inc/dec from the same value, rather than inc/dec by 2. Signed-off-by:
-
Roman Li authored
Added missing reg shift/masks to soc base Signed-off-by:
-
Alex Deucher authored
Until I've had time to test it better. bug: https://bugs.freedesktop.org/show_bug.cgi?id=102372Reviewed-by:
-
Harry Wentland authored
Signed-off-by:
-
Alex Deucher authored
Enable DC for DCE8 APUs. Signed-off-by:
-
Alex Deucher authored
Add the appropriate resources for APUs: KV: 4 pipes, 7 dig, 3 PPLLs KB/ML: 2 pipes, 6 dig, 2 PPLLs v2: rebase changes Signed-off-by:
-
Alex Deucher authored
DCE 8.1 = Kaveri DCE 8.3 = Kabini/Mullins Signed-off-by:
-
Alex Deucher authored
KV has 7 possible DIG blocks. Signed-off-by:
-
Alex Deucher authored
Signed-off-by:
-
Alex Deucher authored
Add DCE8 APUs to display manager. v2: rebase changes Signed-off-by:
-
Alex Deucher authored
Only used in dce120_resource.c. Signed-off-by:
-
Alex Deucher authored
Not used outside of the dce110_resource.c. v2: make a bunch of other functions static as well. Signed-off-by:
-
Harry Wentland authored
Signed-off-by:
-
Harry Wentland authored
This was broken by "implement DXGI Gamma Ramps" Signed-off-by:
-
Harry Wentland authored
Caused by "add programming for 0 plane case" which was tested on DCN but not on DCE. Signed-off-by:
-
Corbin McElhanney authored
(FF-158) -[FF N-1] HDMI Deep Color Mode incorrect bit depth: FMT_DYNAMIC_EXP_EN is being reset to 0 Signed-off-by:
-
Tony Cheng authored
Signed-off-by:
-
Yongqiang Sun authored
Signed-off-by:
-
