- 05 Nov, 2018 40 commits
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Marek Olšák authored
This increases performance of compute queues. EOP events (PKT3_RELEASE_MEM) are stored into these buffers. Signed-off-by:
Marek Olšák <marek.olsak@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Christian König authored
Signal a fault to the scheduler on an illegal instruction or register access violation instead of kicking of the reset handler directly. Signed-off-by:
Christian König <christian.koenig@amd.com> Acked-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Christian König authored
Was never used. Signed-off-by:
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Christian König authored
Add a helper to immediately start timeout handling in case of a hardware fault. Signed-off-by:
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Christian König authored
Make sure we always restart the timer after a timeout and remove the device specific workarounds. Signed-off-by:
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John Clements authored
Revised comments in PSP SOS/Sysdriver loading sequence Signed-off-by:
John Clements <clements.jm@gmail.com> Signed-off-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Philip Yang authored
For sdma v4, there is bug caused by commit d4e869b6b5d6 ("drm/amdgpu: add ring test for page queue")' local variable ring is reused and changed, so amdgpu_ttm_set_buffer_funcs_status(adev, true) is skipped accidently. As a result, amdgpu_fill_buffer() will fail, kernel message: [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260444] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.260627] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290119] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.290370] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.319971] [drm:amdgpu_fill_buffer [amdgpu]] *ERROR* Trying to clear memory with ring turned off. [ 25.320486] amdgpu 0000:19:00.0: [mmhub] VMC page fault (src_id:0 ring:154 vmid:8 pasid:32768, for process pid 0 thread pid 0) [ 25.320533] amdgpu 0000:19:00.0: in page starting at address 0x0000000000000000 from 18 [ 25.320563] amdgpu 0000:19:00.0: VM_L2_PROTECTION_FAULT_STATUS:0x00800134 Signed-off-by:Philip Yang <Philip.Yang@amd.com> Reviewed-by:
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Huang Rui authored
We add page queue for sdma to update page table. So here it also needs ring test to verify it workable during the initialization. Signed-off-by:
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Evan Quan authored
Since we see driver loading failure on Vega20. Keep it disabled until it's ready. Signed-off-by:
Evan Quan <evan.quan@amd.com> Acked-by:
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Alex Deucher authored
Don't use the paging queue on APUs. Tested-by:
Tom St Denis <tom.stdenis@amd.com> Reviewed-by:
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Christian König authored
Only for testing, not sure if we should keep it like this. Signed-off-by:
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Christian König authored
Implement all the necessary stuff to get those extra rings working. Signed-off-by:
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Christian König authored
Significantly shortens the code. Signed-off-by:
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Christian König authored
Just use the same code path for both SRIOV and bare metal. Signed-off-by:
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Christian König authored
Needed to start using the paging queue. Signed-off-by:
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Christian König authored
Just the common helper and a new ring in the SDMA instance. Signed-off-by:
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Christian König authored
Under SRIOV we were enabling the ring buffer before it was initialized. Signed-off-by:
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Thomas Zimmermann authored
So far, struct ttm_bo_global_ref was the only way of initializing a struct ttm_bo_global. Providing separate initializer and release functions for struct ttm_bo_global gives drivers the option of implementing their own init and release callbacks for drm_global_references of type DRM_GLOBAL_TTM_BO. The original functions for initializing and releasing via struct ttm_bo_global_ref are wrappers around the new interfaces. Signed-off-by:
Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by:
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Thomas Zimmermann authored
The functions ttm_bo_global_init() and ttm_bo_global_release() do not receive an argument of type struct ttm_bo_global. Both take a struct drm_global_reference that contains points to a struct ttm_bo_global_ref. Renaming them reflects this. Signed-off-by:
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SivapiriyanKumarasamy authored
Force the E2 to dc_fixpt_one when E1 exceeds that value. This is the correct thing to do to avoid corruption. Signed-off-by:
SivapiriyanKumarasamy <sivapiriyan.kumarasamy@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Signed-off-by:
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Bhawanpreet Lakha authored
cstate_pstate_watermarks_st1 -> cstate_pstate_watermarks_st Signed-off-by:
vikrant mhaske <vikrant.mhaske@amd.com> Signed-off-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Bhawanpreet Lakha authored
explicitly cast uint64_t in div64_u64_rem() Signed-off-by:
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SivapiriyanKumarasamy authored
Signed-off-by:
Harry Wentland <harry.wentland@amd.com> Acked-by:
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Dmytro Laktyushkin authored
This adds the hw block as well as hooks up dppclk dto programming Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
In preparation for adding the actual dccg block since the current implementation of dccg is mor eof a clock manager than a hw block Signed-off-by:
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Fatemeh Darbehani authored
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 2: Separate set_min_deep_sleep_dcfclk message from the SMU messages that are sent as part of dm_pp_apply_clock_for_voltage_request. Directly notify min dcfclk to smu Signed-off-by:
Fatemeh Darbehani <fatemeh.darbehani@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Fatemeh Darbehani authored
[Why] In DCN we want direct DAL to SMU calls, with as little as possible interference by pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in dal and shared across different OS. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 1: Separate set_min_deep_Sleep_dcfclk message from the SMU messages that are sent as part of dcn10_pplib_apply_display_requirements. Notify deep sleep dcfclk to smu directly Signed-off-by:
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Eric Bernstein authored
[Why] Need separate feature flag for DP 4:2:0 support, since existing flag is used for HDMI [How] Added dp_ycbcr420_supported to struct encoder_feature_support Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
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Eric Yang authored
[Why] Previous logic to update display count in commit_planes_do_stream_update doesn't cover all cases. [How] Update display count as part of clock updates. Count virtual stream as active to work around headless situation. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
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Nevenko Stupar authored
Make these functions non static and define registers for future use is_lower_pipe_tree_visible(); is_upper_pipe_tree_visible(); is_pipe_tree_visible(); dcn10_program_pte_vm(); set_hdr_multiplier(); update_dchubp_dpp() find_top_pipe_for_stream() Signed-off-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Reviewed-by:
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David Francis authored
[Why] dc_transfer_func structs were being passed around with a null pointer, waiting for unsuspecting programmers to dereference it. [How] Initialize it Signed-off-by:
David Francis <David.Francis@amd.com> Reviewed-by:
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SivapiriyanKumarasamy authored
[Why] Freesync 2 HDR and support for HDR content outside the range of the HDR display require implementation on Dal 3 to better match Dal2. [How] Add support for Freesync HDR and mapping of source content to display ranges for better representation of HDR content. Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Dmytro Laktyushkin authored
Currently dccg contains code related to every dcn revision in a single file. This change splits out the dcn parts of code into correct folders Signed-off-by:
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Dmytro Laktyushkin authored
Move things not accessed outside dccg block into dce specific struct Signed-off-by:
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Harmanprit Tatla authored
[Why] Current render margin time is not sufficient to compute exit frame time for most monitors. [How] Declared render margin in FPS to compute a exit frame rate that is 4 FPS above the minimum FPS required to engage FreeSync. Also did code clean-up to remove redundancies. Signed-off-by:
Harmanprit Tatla <htatla@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
This is done to keep things more readable, avoids a true/false flag in dc interface layer. Signed-off-by:
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Dmytro Laktyushkin authored
This is done to clear up the clock programming sequence since the only time we need to notify pplib is after clock update. This also renames the clk block to dccg, at the moment this block contains both clock management and dccg functionality. Signed-off-by:
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Dmytro Laktyushkin authored
When vstartup is larger than vblank end we need to set v_fp2 to allow for this early start Signed-off-by:
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Fatemeh Darbehani authored
Signed-off-by:
Steven Chiu <Steven.Chiu@amd.com> Acked-by:
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Frank.Min authored
Reviewed-by:
Frank.Min <Frank.Min@amd.com> Signed-off-by:
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