- 11 Jun, 2013 3 commits
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Olof Johansson authored
Merge tag 'renesas-soc-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Renesas ARM-based SoC updates for v3.11 * Increased clock coverage for r8a7740, r8a73a4, r8a7778 and r8a7790 * Use fixed clock ratio for r8a7778 * Always use shmobile_setup_delay for sh73a0 * Add add CPUFreq support for sh73a0 * Check kick bit before changing rate on sh73a0 * Do not overwrite all div4 clock operations on sh73a0 * Cleanup SH_FIXED_RATIO_CLK and SH_FIXED_RATIO_CLK macros * sh73a0: Use DEFINE_RES_MEM*() everywhere * r8a7740: Make private clock arrays static * r8a7778: Correct model number The last four changes listed above are cleanups. I have included them in this series as all bar the last one are dependencies of non-cleanup patches. * tag 'renesas-soc-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (27 commits) ARM: shmobile: sh73a0: div4 clocks must check the kick bit before changing rate ARM: shmobile: sh73a0: do not overwrite all div4 clock operations ARM: shmobile: sh73a0: Always use shmobile_setup_delay() ARM: shmobile: sh73a0: add CPUFreq support ARM: shmobile: sh73a0: add support for adjusting CPU frequency ARM: shmobile: r8a7790: add TPU PWM support ARM: shmobile: r8a7790: Make private clock arrays static ARM: shmobile: r8a7790: add div6 clocks ARM: shmobile: r8a7790: add div4 clocks ARM: shmobile: r8a7790: add main clock ARM: shmobile: r8a7778: Register SDHI device ARM: shmobile: r8a7778: add SDHI clock support ARM: shmobile: r8a7778: use fixed ratio clock ARM: shmobile: r8a7779: Add PCIe clocks ARM: shmobile: r8a73a4: add div6 clocks ARM: shmobile: r8a73a4: add div4 clocks ARM: shmobile: r8a73a4: add pll clocks ARM: shmobile: r8a73a4: add main clock ARM: shmobile: r8a7740: add TPU PWM support ARM: shmobile: r8a7740: Add I2C DT clock names ... Conflicts: arch/arm/mach-shmobile/Kconfig arch/arm/mach-shmobile/include/mach/r8a7778.h arch/arm/mach-shmobile/setup-r8a7778.c
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Olof Johansson authored
Merge tag 'renesas-pinmux-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc From Simon Horman: Renesas ARM based SoC pinmux and GPIO update for v3.11 SH-PFC: * Entries for INTC external IRQs * Remove dependency on GPIOLIB * PFC support for r8a7790 SoC * Pinmux support for r8a7778 SoC * Increase pin group and function coverage for sh7372, r8a7740, r8a7778, r8a7779 and r8a7790 SoCs * Use pinctrl mapping on mackerel, ap4evb, armadillo800eva, bonito, bockw, lager boards * Use RCAR_GP_PIN macro in marzen board * Remove unused GPIOs for sh7372, sh73a0, r8a7740 and r8a7790 SoCs * Add bias (pull-up/down) pinconf support for r8a7740 SoC * Add VCCQ support for sh73a0 GPIO car: * Add RCAR_GP_PIN macro * Add support for IRQ_TYPE_EDGE_BOTH * Make the platform data gpio_base field signed The GPIO changes have been included as the RCAR_GP_PIN and IRQ_TYPE_EDGE_BOTH changes are depended on by SH-PFC changes. * tag 'renesas-pinmux-for-v3.11' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (132 commits) ARM: shmobile: marzen: Use RCAR_GP_PIN macro ARM: shmobile: lager: Initialize pinmux ARM: shmobile: bockw: add pinctrl support ARM: shmobile: kzm9g: tidyup FSI pinctrl ARM: shmobile: r8a7740 pinmux platform device cleanup ARM: shmobile: r8a7790: Configure R-Car GPIO for IRQ_TYPE_EDGE_BOTH pinctrl: sh-pfc: r8a7779: Fix missing MOD_SEL2 entry Revert "ARM: shmobile: Disallow PINCTRL without GPIOLIB" pinctrl: r8a7790: add pinmux data for MMCIF and SDHI interfaces sh-pfc: r8a7778: add MMCIF pin groups sh-pfc: r8a7778: add HSPI pin groups sh-pfc: r8a7778: add I2C pin groups pinctrl: sh-pfc: fix a typo in pfc-r8a7790 pinctrl: sh-pfc: fix r8a7790 Function Select register tables sh-pfc: r8a7778: fixup IRQ1A settings sh-pfc: r8a7779: add Ether pin groups sh-pfc: r8a7778: add Ether pin groups sh-pfc: r8a7778: add VIN pin groups sh-pfc: sh73a0: Remove function GPIOs sh-pfc: r8a7790: Add TPU pin groups and functions ...
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git://git.infradead.org/users/jcooper/linuxOlof Johansson authored
From Jason Cooper: mvebu pcie driver (kirkwood) for v3.11 (round 2) - kirkwood - migrate Netgear ReadyNAS Duo v2 to pcie DT init * tag 'pcie_kw-3.11-2' of git://git.infradead.org/users/jcooper/linux: arm: kirkwood: NETGEAR ReadyNAS Duo v2 init PCIe via DT Signed-off-by:Olof Johansson <olof@lixom.net>
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- 08 Jun, 2013 1 commit
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git://git.xilinx.com/linux-xlnxOlof Johansson authored
From Michal Simek: arm: Xilinx Zynq clock changes for v3.11 Change Xilinx Zynq DT clock description which reflects logical abstraction of Zynq's clock tree. - Refactor PLL driver - Use new clock controller driver - Change timer and uart drivers * tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx: clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by:
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- 07 Jun, 2013 24 commits
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Guennadi Liakhovetski authored
According to the datasheet, it is not allowed to change div4 clock rates if an earlier rate change operation is still in progress, as indicated by a set kick bit. Signed-off-by:
Guennadi Liakhovetski <g.liakhovetski+renesas@gmail.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Guennadi Liakhovetski authored
An earlier commit "ARM: shmobile: sh73a0: add support for adjusting CPU frequency" intended to replace some clock operations only for the Z-clock, instead it replaced them for all div4 clocks, since all div4 clocks share the same copy of clock operations. Fix this by using a separate clock operations structure for Z-clock. Signed-off-by:
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Magnus Damm authored
Break out the function sh73a0_init_delay() that now gets called both for the C version of the code and the DT -reference boards. This way we handle both cases in the same way. Allows us to boot with TWD only in the kernel configuration for C board code. TWD is not yet enabled in the case of DT -reference - this due to a dependency on CCF. Signed-off-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Guennadi Liakhovetski authored
This patch enables the use of the generic cpufreq-cpu0 driver on sh73a0. Providing a regulator, a list of OPPs in DT, combined with a virtual cpufreq-cpu0 platform device and a clock, attached to it is everything, the cpufreq-cpu0 driver needs. The first sh73a0 platform, implementing such CPUFreq support is kzm9g-reference. Signed-off-by:
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Guennadi Liakhovetski authored
On SH73A0 the output of PLL0 is supplied to two dividers, feeding clock to the CPU core and SGX. Lower CPU frequencies allow the use of lower supply voltages and thus reduce power consumption. Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. Signed-off-by:
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Kuninori Morimoto authored
DIV6 clocks control SD*/MMC* core clocks. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
DIV4 clocks control SD* core clocks. Signed-off-by:
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Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a7790. This patch adds it, and, set its parent/ratio via MD pin. It is based on v0.05 datasheet Signed-off-by:
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Kuninori Morimoto authored
This patch adds SDHI register function which needs id number (= 0/1/2) Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Kuninori Morimoto authored
R-Car M1 has many clocks, and it is possible to read/use clock ratio of these clocks from FRQMRx. But, these ratio are fixed value and these are decided by MD pin status. This patch reads MD pin status, and used fixed ratio clock for other clocks. It was tesed on bock-w board. Signed-off-by:
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Phil Edworthy authored
Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
DIV6 clocks control each core clocks. Signed-off-by:
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Kuninori Morimoto authored
DIV4 clocks control each core clocks. Signed-off-by:
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Kuninori Morimoto authored
PLL clocks are basis clock for other clock. Signed-off-by:
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Kuninori Morimoto authored
Almost all clock needs main clock which is basis clock on r8a73a4. This patch adds it, and, set parent clock via CKSCR register. Signed-off-by:
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Laurent Pinchart authored
Signed-off-by:
Simon Horman <horms@verge.net.au> Signed-off-by:
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Bastian Hecht authored
Add clock association for i2c0 and i2c1 for the new DT names. Signed-off-by:
Bastian Hecht <hechtb+renesas@gmail.com> Signed-off-by:
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Bastian Hecht authored
When we use the ethernet device via DT setup, we need to add it to a lookup list until this is properly handled later in a DT-only fashion. Signed-off-by:
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Kuninori Morimoto authored
Ether setup code position was scattering. This patch fixes it up Signed-off-by:
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Kuninori Morimoto authored
SH_CLK_SET_RATIO() will be trouble without this patch Signed-off-by:
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Kuninori Morimoto authored
Acked-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by:
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- 06 Jun, 2013 3 commits
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Simon Horman authored
Convert code to use DEFINE_RES_MEM*() macros. These macros were already used in this file, this change makes their usage consistent throughout the file. Signed-off-by: -
Sergei Shtylyov authored
The correct model name is R-Car M1A or R8A77781; R8A77780 corresponds to R-Car M1S which is a SH based SoC. Signed-off-by:
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Laurent Pinchart authored
Both clock-r8a7740.c and clock-r8a7790.c define a div4_clks array as non-static. Compiling support for both SoCs thus result in a symbol redefinition. Fix it by defining the arrays as static. To avoid further similar issues, also define the main_clks as static. Signed-off-by:
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- 05 Jun, 2013 9 commits
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Laurent Pinchart authored
Replace hardcoded pin numbers with the RCAR_GP_PIN macro to make the code match the documentation. Signed-off-by:
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Laurent Pinchart authored
Initialize r8a7790 pinmuxing and register mappings for the two debug serial ports. Signed-off-by:
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Kuninori Morimoto authored
SCIF0 support as 1st step Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Kuninori Morimoto authored
sh73a0 needs "sh_fsi2", not "sh_fsi2.0" Tested-by:
Hiep Cao Minh <cm-hiep@jinso.co.jp> Acked-by:
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Magnus Damm authored
Use DEFINE_RES_MEM() and platform_device_register_simple() to save a couple of lines of code. Signed-off-by:
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Simon Horman authored
"gpio-rcar: Support IRQ_TYPE_EDGE_BOTH" adds support to the R-Car GPIO driver for IRQ_TYPE_EDGE_BOTH. As hardware support for this feature is not universal for all SoCs a flag, has_both_edge_trigger, has been added to the platform data of the driver to allow this feature to be enabled. As the r8a7790 SoC hardware supports this feature enable it. Signed-off-by: -
Phil Edworthy authored
The list of functions selected by the MOD_SEL2 register was missing an entry. This caused all entries after this to modify the MOD_SEL2 register incorrectly. This bug showed up when selecting i2c2_c pins on the Renesas Hurricane board. This bug has been present since pinmux support was added for the r8a7779 SoC by 881023d2 ("sh-pfc: Add r8a7779 pinmux support") in v3.8-rc4. Signed-off-by:
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Laurent Pinchart authored
GPIOLIB dependency handling was added to the PINCTRL core by commit 2afe8229 Author: Haojian Zhuang <haojian.zhuang@linaro.org> Date: Thu Mar 28 07:34:19 2013 +0800 pinctrl: core: add dependence of GPIOLIB There is not need to handle that dependency at the SH Mobile level anymore. Revert commit 6722f6cb Author: Magnus Damm <damm@opensource.se> Date: Mon Mar 18 22:58:18 2013 +0900 ARM: shmobile: Disallow PINCTRL without GPIOLIB Modify mach-shmobile to only select PINCTRL in case of ARCH_WANT_OPTIONAL_GPIOLIB is set. This fixes a build error triggered when adding a new SoC lacking GPIO software support (ARCH_WANT_OPTIONAL_GPIOLIB=n): Signed-off-by:
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Guennadi Liakhovetski authored
This patch adds pinmux groups and functions for the two MMCIF and four SDHI interfaces on r8a73a4 (APE6). Signed-off-by:
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