- 25 Jul, 2014 2 commits
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Thomas Petazzoni authored
Following the merging of mach-kirkwood into mach-mvebu, the removal of mach-kirkwood, and the progress of the integration of mach-dove into mach-mvebu, this commit makes a few updates to the Marvell README file in the kernel documentation. Signed-off-by:
Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Acked-by:
Andrew Lunn <andrew@lunn.ch> Link: https://lkml.kernel.org/r/1406227593-29749-3-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by:
Jason Cooper <jason@lakedaemon.net>
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Thomas Petazzoni authored
Marvell has very recently released a public version of the "Functional specifications" and "Hardware specifications" datasheets for the Marvell Armada XP SoC. This allows contributors and developers not under NDA with Marvell to get more details about this SoC than what the current kernel code shows, and hopefully allows to improve the support for this SoC in the mainline kernel, as well as in other projects. Signed-off-by:
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- 24 Jul, 2014 17 commits
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Arnd Bergmann authored
When building a multiplatform kernel that enables 'ARCH_MVEBU' but none of the individual options under it, we get this link error: arch/arm/mach-mvebu/built-in.o: In function `mvebu_armada375_smp_wa_init': :(.text+0x190): undefined reference to `mvebu_setup_boot_addr_wa' The best solution seems to be to ensure that in this configuration, we don't actually build any of the mvebu code. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Link: https://lkml.kernel.org/r/7339332.ZE2mWIdyDh@wuerfelSigned-off-by:
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Jason Cooper authored
Conflicts: arch/arm/mach-mvebu/pmsu.c
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Gregory CLEMENT authored
Unlike the Armada XP and the Armada 370, this SoC uses a Cortex A9 core. Consequently, the procedure to enter the idle state is different: interaction with the SCU, not disabling snooping, etc. Signed-off-by:
Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by:
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Gregory CLEMENT authored
This commit introduces the cpuidle support for Armada 370. The main difference compared to the already supported Armada XP is that the Armada 370 has an issue caused by "a slow exit process from the deep idle state due to heavy L1/L2 cache cleanup operations performed by the BootROM software" (cf errata GL-BootROM-10). To work around this issue, we replace the restart code of the BootROM by some custom code located in an internal SRAM. For this purpose, we use the common function mvebu_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around". The message in case of failure to suspend the system was switched from the warn level to the debug level. Indeed due to the "slow exit process from the deep idle state" in Armada 370, this situation happens quite often. Using the debug level avoids spamming the kernel logs, but still allows to enable it if needed. Signed-off-by:
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Thomas Petazzoni authored
This commit adds the list of cpuidle states supported by the Armada 38x SoC in the cpuidle-mvebu-v7 driver, as well as the necessary logic around it to support this SoC. Signed-off-by:
Daniel Lezcano <daniel.lezcano@linaro.org> Link: https://lkml.kernel.org/r/1406120453-29291-14-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by:
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Thomas Petazzoni authored
This commit adds the list of cpuidle states supported by the Armada 370 SoC in the cpuidle-mvebu-v7 driver, as well as the necessary logic around it to support this SoC. Signed-off-by:
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Gregory CLEMENT authored
This driver will be able to manage the cpuidle for more SoCs than just Armada 370 and XP. It will also support Armada 38x and potentially other SoC of the Marvell Armada EBU family. To take this into account, this patch renames the driver and its symbols. It also changes the driver name from cpuidle-armada-370-xp to cpuidle-armada-xp, because separate platform drivers will be registered for the other SoC types. This change must be done simultaneously in the cpuidle driver and in the PMSU code in order to remain bisectable. Signed-off-by:
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Gregory CLEMENT authored
The SCU address will be needed in other files than board-v7.c, especially in pmsu.c for cpuidle related activities. So this patch adds a function that allows to retrieve the virtual address at which the SCU has been mapped. Signed-off-by:
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Gregory CLEMENT authored
On some mvebu v7 SoCs (the ones using a Cortex-A9 core and not a PJ4B core), the snoop disabling feature does not exist as the hardware coherency is handled in a different way. Therefore, in preparation to the introduction of the cpuidle support for those SoCs, this commit modifies the mvebu_v7_psmu_idle_prepare() function to take several flags, which allow to decide whether snooping should be disabled, and whether we should use the deep idle mode or not. Signed-off-by:
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Gregory CLEMENT authored
The resume address used by the cpuidle code will not always be the same depending on the SoC. Using a local variable to store the resume address allows to keep the same function for the PM notifier but with a different address. This address will be set during the initialization of the cpuidle logic in pmsu.c. Signed-off-by:
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Gregory CLEMENT authored
In preparation to the addition of the cpuidle support for more SoCs, this patch moves the Armada XP specific initialization to a separate function. Signed-off-by:
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Gregory CLEMENT authored
Most of the function related to the PMSU are not specific to the Armada 370 or Armada XP SoCs. They can also be used for most of the other mvebu ARMv7 SoCs, and will actually be used to support cpuidle on Armada 38x. Signed-off-by:
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Gregory CLEMENT authored
Use the common function mvebu_setup_boot_addr_wa() introduced in the commit "ARM: mvebu: Add a common function for the boot address work around" instead of the dedicated version for Armada 375. This commit also moves the workaround in the system-controller module. Indeed the workaround on 375 is really related to setting the boot address which is done by the system controller. As a bonus we no longer use an harcoded value to access the register storing the boot address. Signed-off-by:
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Gregory CLEMENT authored
On some of the mvebu SoCs and due to internal BootROM issue, the CPU initial jump code must be placed in the SRAM memory of the SoC. In order to achieve this, we have to unmap the BootROM and at some specific location where the BootROM was placed, create a dedicated MBus window for the SRAM. This SRAM is initialized with a few instructions of code that allows to jump to the real secondary CPU boot address. The SRAM used is the Crypto engine one. This work around is currently needed for booting SMP on Armada 375 Z1 and will be needed for cpuidle support on Armada 370. Instead of duplicating the same code, this commit introduces a common function to handle it: mvebu_setup_boot_addr_wa(). Signed-off-by:
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Gregory CLEMENT authored
Sorting the headers in alphabetic order will help to reduce conflicts when adding new headers later. Signed-off-by:
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Gregory CLEMENT authored
do_armada_370_xp_cpu_suspend() and armada_370_xp_pmsu_idle_prepare(), have been merged into a single function called armada_370_xp_pmsu_idle_enter() by the commit "bbb92284 ARM: mvebu: slightly refactor/rename PMSU idle related functions", in prepare for the introduction of the CPU hotplug support for Armada XP. But for cpuidle the prepare function will be common to all the mvebu SoCs that use the PMSU, while the suspend function will be specific to each SoC. Keeping the prepare function separate will help reducing code duplication while new SoC support is added. Signed-off-by:
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Jason Cooper authored
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- 23 Jul, 2014 1 commit
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Wei Yongjun authored
In case of error, the function clk_get() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Signed-off-by:
Wei Yongjun <yongjun_wei@trendmicro.com.cn> Link: https://lkml.kernel.org/r/1406038688-26417-1-git-send-email-weiyj_lk@163.comSigned-off-by:
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- 22 Jul, 2014 1 commit
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Jason Cooper authored
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- 16 Jul, 2014 3 commits
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Thomas Petazzoni authored
This commit extends the existing clk-cpu driver used on Marvell Armada XP platforms to support the dynamic frequency scaling of the CPU clock. Non-dynamic frequency change was already supported (and used before secondary CPUs are started), but the dynamic frequency change requires a completely different procedure. In order to achieve this, the clk_cpu_set_rate() function is reworked to handle two separate cases: - The case where the clock is enabled, which is the new dynamic frequency change code, implemented in clk_cpu_on_set_rate(). This part will be used for cpufreq activities. - The case where the clock is disabled, which is the existing frequency change code, moved in clk_cpu_off_set_rate(). This part is already used to set the clock frequency of the secondary CPUs before starting them. In order to implement the dynamic frequency change function, we need to access the PMU DFS registers, which are outside the currently mapped "Clock Complex" registers, so a new area of registers is now mapped. This affects the Device Tree binding, but we are careful to do it in a backward-compatible way (by allowing the second pair of registers to be non-existent, and in this case, ensuring clk_cpu_on_set_rate() returns an error). Note that technically speaking, the clk_cpu_on_set_rate() does not do the entire procedure needed to change the frequency dynamically, as it involves touching a number of PMSU registers. This is done through a clock notifier registered by the PMSU driver in followup commits. Cc: <devicetree@vger.kernel.org> Signed-off-by:
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Thomas Petazzoni authored
This commit adds the necessary code in the Marvell EBU PMSU driver to support dynamic frequency scaling. In essence, what this new code does is that it: * registers the frequency operating points supported by the CPU; * registers a clock notifier of the CPU clocks. The notifier function listens to the newly introduced APPLY_RATE_CHANGE event, and uses that to finalize the frequency transition by doing the part of the procedure that involves the PMSU; * registers a platform device for the cpufreq-generic driver, which will take care of the CPU frequency transitions. Signed-off-by:
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Thomas Petazzoni authored
In the Armada XP SMP support code, we are reading the clock frequency of the booting CPU, and use that to assign the same frequency to the other CPUs, and we do this while the clocks are disabled. However, the CPU clocks are in fact never prepared/enabled, and to support cpufreq, we now have two code paths to change the frequency of the CPU clocks in the CPU clock driver: one when the clock is enabled (dynamic frequency scaling), one when the clock is disabled (adjusting the CPU frequency before starting the CPU). In order for this to work, the CPU clocks now have to be prepared and enabled after the initial synchronization of the clock frequencies is done, so that all future rate changes of the CPU clocks will trigger a dynamic frequency scaling transition. Signed-off-by:
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- 13 Jul, 2014 1 commit
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Andrew Lunn authored
Now that all boards have been converted to DT and all the support code lives in mach-mvebu, we can remove mach-kirkwood. Signed-off-by:
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- 08 Jul, 2014 2 commits
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Ezequiel Garcia authored
Currently, the coherency fabric support registers two bus notifiers; one for platform, one for pci bus types, with the same notifier block. However, this is illegal and can cause serious issues: the notifier block is also a link in the notifier list and cannot be inserted twice. This commit fixes this by using different notifier blocks (with the same notifier callback) to set the platform and pci bus types notifiers. Fixes: b0063aad ("ARM: mvebu: use hardware I/O coherency also for PCI devices") Reported-by:
Paolo Pisati <p.pisati@gmail.com> Signed-off-by:
Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1404826657-6977-1-git-send-email-ezequiel.garcia@free-electrons.comSigned-off-by:
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Gregory CLEMENT authored
In the inline asm part of the function armada_370_xp_pmsu_idle_enter() the input operand was used. The intent here was to let the compiler choose this register so it could do the optimization it needed. However an input operand is not supposed to be modified by the inline asm code. This can lead to improper generated instructions. In some case generated instruction the compiler made the choice to reuse the same register to store the return value. But in the assembly part this register was modified, so it can lead to return an wrong value. The fix is to use a clobber. Thanks to this the compiler will know that the value of this register will be modified. Signed-off-by:
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- 01 Jul, 2014 1 commit
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Thomas Petazzoni authored
The SMP boot on Armada 38x and Armada 375 Z1 is currently broken in big-endian configurations, and this commit fixes it for both platforms. For Armada 375 Z1, the problem was in the armada_375_smp_cpu1_enable_code part of the code that gets copied to the Crypto SRAM as a work-around for an issue of the Z1 stepping. This piece of code was not switching the CPU core to big-endian, and not endian-swapping the value read from the Resume Address register (the value is stored little-endian). Due to the introduction of the conditional 'rev r1, r1' instruction, the offset between the 'ldr r0, [pc, #4]' instruction and the value it was looking is different between LE and BE configurations. To solve this, we instead use one 'adr' instruction followed by one 'ldr'. For Armada 38x, the problem was simply that the CPU core was not switched to big endian in the secondary CPU startup function. This change was tested in LE and BE configurations on Armada 385, Armada 375 Z1 and Armada 375 A0. Signed-off-by:
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- 30 Jun, 2014 8 commits
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Thomas Petazzoni authored
On Marvell Armada XP, when a CPU comes back from deep idle state of cpuidle, it restarts its execution at armada_370_xp_cpu_resume(), which puts back the CPU into the coherency, and then calls the generic cpu_resume() function. While this works on little-endian configurations, it doesn't work on big-endian configurations because the CPU restarts in little-endian, and therefore must be switched back to big-endian to operate properly. To achieve this, a 'setend be' instruction must be executed in big-endian configurations. However, the ARM_BE8() macro that is used to implement nice compile-time conditional for ARM LE vs. ARM BE8 is not easily usable in inline assembly. Therefore, this patch moves the armada_370_xp_cpu_resume() C function, which was anyway just a block of inline assembly, into a proper pmsu_ll.S file, and adds the appropriate ARM_BE8(setend be) instruction. Without this patch, an Armada XP big endian configuration with cpuidle enabled fails to boot, as it hangs as soon as one of the CPU hits the deep idle state. Signed-off-by:
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Sachin Kamat authored
'mvebu_cpu_reset_init' is local to this file. Signed-off-by:
Sachin Kamat <sachin.kamat@linaro.org> Link: https://lkml.kernel.org/r/1403610235-22654-4-git-send-email-sachin.kamat@samsung.comSigned-off-by:
Sachin Kamat <sachin.kamat@samsung.com> Acked-by:
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Sachin Kamat authored
'armada_370_xp_cpu_pm_init' is local to this file. Signed-off-by:
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Sachin Kamat authored
'armada_375_smp_cpu1_enable_wa' is local to this file. Signed-off-by:
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Gregory CLEMENT authored
On Armada 38x it is possible to get the SoC Id and the revision without using the PCI register. Accessing the PCI registers implies enabling its clock and, because of the initialization issue, not keeping them enable. So if possible it is better to avoid it. Armada 370 and Armada XP provides the SoC ID values from the system controller but not the revision. Armada 375 provides both but the SoC ID value looks buggy (0x6660 instead of 0x6720). Signed-off-by:
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Gregory CLEMENT authored
Instead of using -1 as error value, use a standard errno. Signed-off-by:
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Thomas Petazzoni authored
Commit 497a9230 ("ARM: mvebu: implement L2/PCIe deadlock workaround") introduced some logic in coherency.c to adjust the PL310 cache controller Device Tree node of Armada 375 and Armada 38x platform to include the 'arm,io-coherent' property if the system is running with hardware I/O coherency enabled. However, with the L2CC driver cleanup done by Russell King, the initialization of the L2CC driver has been moved earlier, and is now part of the init_IRQ() ARM function in arch/arm/kernel/irq.c. Therefore, calling coherency_init() in ->init_time() is now too late, as the Device Tree property gets added too late (after the L2CC driver has been initialized). In order to fix this, this commit removes the ->init_time() callback use in board-v7.c and replaces it with an ->init_irq() callback. We therefore no longer use the default ->init_irq() callback, but we now use the default ->init_time() callback. In this newly introduced ->init_irq() callback, we call irqchip_init() which is the default behavior when ->init_irq() isn't defined, and then do the initialization related to the coherency: SCU, coherency fabric, and mvebu-mbus (which is needed to start secondary CPUs). Signed-off-by:
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Thomas Petazzoni authored
In preparation to a small re-organization of the initialization sequence in board-v7.c, this commit moves the registration of the custom external abort handler on Armada 375 later in the boot sequence, and makes it more similar to the other quirks that we already have. There is indeed no need to register this abort handler particularly early, it simply needs to be registered before switching to userspace. In addition to this, this commit makes the registration of the custom abort handler conditional on Armada 375 Z1, because Armada 375 A0 and later iterations are not affected by the issue. This commit was tested on both Armada 375 Z1 and Armada 375 A0 platforms. Signed-off-by:
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- 24 Jun, 2014 1 commit
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Gregory CLEMENT authored
Wildcards in compatible strings should be avoid. "marvell,armada38x" was recently introduced but was not yet used. The armada 385 SoC is a superset of the armada 380 SoC (with more CPUs and more PCIe slots). So this patch replaces the use of "marvell,armada38x" by the "marvell,armada380" string. Signed-off-by:
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- 23 Jun, 2014 1 commit
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Sebastian Hesselbarth authored
Commit eeb84545 ("ARM: dts: kirkwood: set Guruplug phy-connection-type to rgmii-id") added phy-connection-type properties to ethernet PHY nodes. Actually, the property has to be set for the ethernet port node instead. Fix it by moving the corresponding properties to the correct nodes. Signed-off-by:
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- 21 Jun, 2014 2 commits
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Ezequiel Garcia authored
Currently, the thermal quirk is skipped only if the SoC revision is known to be one that does not need them, but if the SoC revision cannot be obtained, the quirk is applied assuming it's needed. However, this quirk must be applied only we are sure the SoC needs it, for it breaks the thermal support if applied on a SoC that doesn't need it. The reason for this is that the quirk consists in changing the thermal devicetree compatible string and register offsets, to workaround a hardware bug in the early SoC revision. Such changes are wrong if the SoC is a new revision and doesn't need the workaround. Therefore, this commit changes the behavior, by requiring the SoC revision to be known in order to peform a quirk. Signed-off-by:
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Thomas Petazzoni authored
Marvell has very recently released a public version of the "Functional specifications" and "Hardware specifications" datasheets for the Marvell Armada 370 SoC. This allows contributors and developers not under NDA with Marvell to get more details about this SoC than what the current kernel code shows, and hopefully allows to improve the support for this SoC in the mainline kernel, as well as in other projects. Signed-off-by:
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