- 21 Nov, 2016 3 commits
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Ladislav Michl authored
Move urb killing code into separate function and use it instead of copying that code pattern over. Signed-off-by:
Ladislav Michl <ladis@linux-mips.org> Acked-by:
Oliver Neukum <oneukum@suse.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Ladislav Michl authored
Pointer to usb_device is already stored in acm structure. Signed-off-by:
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Ladislav Michl authored
Use only one tab to indent dev_{(v)dbg,err} parameters. Signed-off-by:
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- 18 Nov, 2016 37 commits
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usbGreg Kroah-Hartman authored
Felipe writes: usb: patches for v4.10 merge window One big merge this time with a total of 166 non-merge commits. Most of the work, by far, is on dwc2 this time (68.2%) with dwc3 a far second (22.5%). The remaining 9.3% are scattered on gadget drivers. The most important changes for dwc2 are the peripheral side DMA support implemented by Synopsys folks and support for the new IOT dwc2 compatible core from Synopsys. In dwc3 land we have support for high-bandwidth, high-speed isochronous endpoints and some non-critical fixes for large scatter lists. Apart from these, we have our usual set of cleanups, non-critical fixes, etc.
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Felix Hädicke authored
Add check for NULL before calling kthread_stop(). There were cases in which gserial_console_exit() was called, but the console thread was not started. This resulted in an invalid kthread_stop(NULL) call. Without this, the following Oops may occur: BUG: unable to handle kernel NULL pointer dereference at 0000000000000018 IP: [<ffffffffb3ca1166>] kthread_stop+0x16/0x110 ... CPU: 2 PID: 853 Comm: rmmod Not tainted 4.9.0-rc5 #3 Hardware name: To Be Filled By O.E.M. To Be Filled By O.E.M./Z77 Extreme3, BIOS P1.50 07/11/2013 task: ffff880419f6a100 task.stack: ffffc90002e8c000 RIP: 0010:[<ffffffffb3ca1166>] [<ffffffffb3ca1166>] kthread_stop+0x16/0x110 RSP: 0018:ffffc90002e8fdb0 EFLAGS: 00010286 RAX: 0000000000000001 RBX: 0000000000000000 RCX: 0000000000000000 RDX: 0000000000000001 RSI: 0000000000000246 RDI: 0000000000000000 RBP: ffffc90002e8fdc8 R08: 0000000000000000 R09: 0000000000000001 R10: 000000000000019d R11: 000000000000001f R12: 0000000000000000 R13: ffff88041b8d8400 R14: 0000000000000001 R15: 000055fd59f5a1e0 FS: 00007f82500be700(0000) GS:ffff88042f280000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000018 CR3: 000000041bee2000 CR4: 00000000001406e0 Stack: 0000000000000000 ffffffffc0b8e720 ffff88041b8d8400 ffffc90002e8fdf0 ffffffffc0b8bb52 ffff88041a106300 0000000000000001 ffff880419fc2ea8 ffffc90002e8fe08 ffffffffc0aed749 ffffffffc0aef600 ffffc90002e8fe20 Call Trace: [<ffffffffc0b8bb52>] gserial_free_line+0x72/0xb0 [u_serial] [<ffffffffc0aed749>] acm_free_instance+0x19/0x30 [usb_f_acm] [<ffffffffc0b01b40>] usb_put_function_instance+0x20/0x30 [libcomposite] [<ffffffffc04a603b>] gs_unbind+0x3b/0x70 [g_serial] [<ffffffffc0b018d1>] __composite_unbind+0x61/0xb0 [libcomposite] [<ffffffffc0b01933>] composite_unbind+0x13/0x20 [libcomposite] [<ffffffffc08ef1ad>] usb_gadget_remove_driver+0x3d/0x90 [udc_core] [<ffffffffc08ef26e>] usb_gadget_unregister_driver+0x6e/0xc0 [udc_core] [<ffffffffc0aff6d2>] usb_composite_unregister+0x12/0x20 [libcomposite] [<ffffffffc04a6268>] cleanup+0x10/0xda8 [g_serial] [<ffffffffb3d0c0c2>] SyS_delete_module+0x192/0x270 [<ffffffffb3c032a0>] ? exit_to_usermode_loop+0x90/0xb0 [<ffffffffb4228a3b>] entry_SYSCALL_64_fastpath+0x1e/0xad Code: 89 c6 e8 6e ff ff ff 48 89 df e8 06 bd fd ff 5b 5d c3 0f 1f 00 0f 1f 44 00 00 55 48 89 e5 41 55 41 54 49 89 fc 53 0f 1f 44 00 00 <f0> 41 ff 44 24 18 4c 89 e7 e8 bc f1 ff ff 48 85 c0 48 89 c3 74 RIP [<ffffffffb3ca1166>] kthread_stop+0x16/0x110 RSP <ffffc90002e8fdb0> CR2: 0000000000000018 ---[ end trace 5b3336a407e1698c ]--- Signed-off-by:Felix Hädicke <felixhaedicke@web.de> Tested-by:
Peter Chen <peter.chen@nxp.com> Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com>
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Arnd Bergmann authored
The dma mask is correctly set up by the DT probe function, no need to override it any more. Signed-off-by:
Arnd Bergmann <arnd@arndb.de> Signed-off-by:
Sriram Dash <sriram.dash@nxp.com> Signed-off-by:
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Arnd Bergmann authored
The dma ops for dwc3 devices are not set properly. So, use a physical device sysdev, which will be inherited from parent, to set the hardware / firmware parameters like dma. Signed-off-by:
Baolin Wang <baolin.wang@linaro.org> Signed-off-by:
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Arnd Bergmann authored
Building with W=1, we get a warning about harmless empty statements: drivers/usb/dwc3/ep0.c: In function 'dwc3_ep0_handle_intf': drivers/usb/dwc3/ep0.c:491:4: error: suggest braces around empty body in an 'if' statement [-Werror=empty-body] Instead of adding empty braces which would introduce checkpatch.pl warnings, we're just removing the code which doesn't do anything and making sure we return 0 so USBCV tool is happy. Signed-off-by:
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Razmik Karapetyan authored
Removed extern specifier from dwc2_host_start(), dwc2_host_disconnect() and dwc2_host_hub_info() functions. Moved those functions from header to source. Then make them static. Signed-off-by:
Razmik Karapetyan <razmik@synopsys.com> Signed-off-by:
John Youn <johnyoun@synopsys.com> Signed-off-by:
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Razmik Karapetyan authored
NPTXFIFO's start address is showing 0x03000000 instead of 0x00000800. Replaced val & FIFOSIZE_DEPTH_MASK by val & FIFOSIZE_STARTADDR_MASK in fifo_show() function. Signed-off-by:
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Razmik Karapetyan authored
Remove request length checking from dwc2_hsotg_unmap_dma() and dwc2_hsotg_map_dma(). That checking is done in functions called from those functions, usb_gadget_unmap_request_by_dev() and usb_gadget_map_request_by_dev() respectively, so it's unnecessary. Signed-off-by:
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Razmik Karapetyan authored
While sending zlp for DWC2_EP0_STATUS_IN EP direction was changed to IN. Change it back to complete OUT transfer request. This affects only on DMA mode, because DMA buffer map/unmap function is direction sensitive. Signed-off-by:
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Razmik Karapetyan authored
Check the request length in dwc2_hsotg_start_req() function. If length == 0, do not write DMA address to control register. Signed-off-by:
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Sevak Arakelyan authored
Stop sending complete split requests in case of ISOC IN split transfers after getting data with PID0. Otherwise we will get a NYET for each additional IN token. Signed-off-by:
Sevak Arakelyan <sevaka@synopsys.com> Signed-off-by:
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Felipe Balbi authored
dwc3_pci_dsm() is only needed if (PM || PM_SLEEP), we should make sure it's not defined if neither of those is defined. This fixes a randconfig build warning. Acked-by:
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John Youn authored
This is a workaround for STAR 9000961433 which affects only version 3.00a of the DWC_usb3 core. This prevents the controller interrupt from being masked while handling events. Enabling interrupt moderation allows us to work around this issue because once the GEVNTCOUNT.count is written the IRQ is immediately deasserted and won't be asserted again until GEVNTCOUNT.EHB is cleared. Signed-off-by:
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John Youn authored
Implement interrupt moderation which allows the interrupt rate to be throttled. To enable this feature the dwc->imod_interval must be set to 1 or greater. This value specifies the minimum inter-interrupt interval, in 250 ns increments. A value of 0 disables interrupt moderation. This applies for DWC_usb3 version 3.00a and higher and for DWC_usb31 version 1.20a and higher. Signed-off-by:
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Christian Lamparter authored
This patch adds support for the "amcc,usb-otg" device which is found in the PowerPC Canyonlands' dts. The device definition was added by: commit c89b3458 ("powerpc/44x: Add USB DWC DTS entry to Canyonlands board") but without any driver support as the dwc2 driver wasn't available at that time. Note: The system can't use the generic "snps,dwc2" compatible because of the special ahbcfg configuration. The default GAHBCFG_HBSTLEN_INCR4 of snps,dwc2 can cause a system hang when the USB and SATA is used concurrently. Signed-off-by:
Christian Lamparter <chunkeey@gmail.com> Signed-off-by:
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Christian Lamparter authored
This patch moves the the host_dma initialization before dwc2_set_param_dma_desc_enable() and dwc2_set_param_dma_desc_fs_enable(). The reason being that both function need it. Fixes: 1205489cee75bf39 ("usb: dwc2: Get host DMA device properties") Acked-by: -
Vardan Mikayelyan authored
Added new core param for low speed, which can be used only when SNPSID is equal to DWC2_CORE_FS_IOT. When LS mode is enabled, we are restricting ep types and providing to upper layer only INTR and CTRL endpoints. Signed-off-by:
Vardan Mikayelyan <mvardan@synopsys.com> Signed-off-by:
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Vardan Mikayelyan authored
When device is enumerated in LS we should program ep0_mps accordingly. USB2 spec says that in LS mode, control ep mps must be 8. Signed-off-by:
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Vardan Mikayelyan authored
Add new device IDs for IOT gadget. Done changes in probe to configure core accordingly depending on device ID value. Signed-off-by:
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Vahram Aharonyan authored
Do modifications in dwc2_hsotg_core_init_disconnected() function to enable USB 1.1 Full-Speed Serial Transceiver Select in GUSBCFG register if corresponding speed and PHY types are chosen. Adjust device speed selection in DCFG register as well. Signed-off-by:
Vahram Aharonyan <vahrama@synopsys.com> Signed-off-by:
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Vahram Aharonyan authored
Check if endpoint is enabled during dwc2_hsotg_ep_disable() function processing and call dwc2_hsotg_ep_stop_xfr() to disable it and flush associated FIFO. Move dwc2_hsotg_ep_stop_xfr() and dwc2_hsotg_wait_bit_set() functions upper before dwc2_hsotg_ep_enable and dwc2_hsotg_ep_disable function definitions. Signed-off-by:
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Vahram Aharonyan authored
Correct dwc2_hsotg_ep_stop_xfr() function to follow dwc2 programming guide for setting NAK on specific endpoint, disabling it and flushing corresponding FIFO. Current code does not take into account whether core acts in shared or dedicated FIFO mode, current endpoint is periodic or not. It does not clear EPDISBLD interrupt after programming of DXEPCTL_EPDIS, does not flush shared TX FIFO and tries to clear global out NAK in wrong manner instead of setting DCTL_CGOUTNAK. Signed-off-by:
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Vahram Aharonyan authored
Tests with various hosts show that depend on time difference between host sending SETUP packet and IN/OUT token SW could get Xfercomplete interrupt without SetUp interrupt. On the other hand, SW should parse received SETUP packet only after ensuring that Host has moved to either Data or Status stage of control transfer. For this purpose added checking in the dwc2_hsotg_epint() function to not handle xfercomplete and postpone SETUP packet analysis till SW's getting of setup phase done interrupt. Signed-off-by:
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Vahram Aharonyan authored
In DDMA mode if programmed ISOC OUT transfer length is not DWORD aligned, after closing descriptor HW leaves value of 4 - (ureq->length % 4) in the RX bytes. This is caused because DMA works using 4B chunks. Example: if length = 9 and all 9 bytes were received from the bus, after xfercomplete rx_bytes value is 3. Hence add this value to the amount of transferred bytes. Signed-off-by:
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Vahram Aharonyan authored
Enable the BNA (Buffer Not Available) interrupt in descriptor DMA mode. Signed-off-by:
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Vahram Aharonyan authored
For DDMA mode in case of isochronous transfers completion performed differently than other transfer types. This is because each usb request was mapped to one descriptor in the chain and SW gets xfercomplete interrupt on all descriptors. The endpoint remains enabled until HW processes last descriptor with "L" bit set or BNA interrupt gets asserted for IN and OUT endpoints correspondingly. Add function dwc2_gadget_complete_isoc_request_ddma() - completes one isochronous request taken from endpoint's queue. Add function dwc2_gadget_start_next_isoc_ddma() - tries to restart isochronous endpoint if requests are pending. Check for EPENA. If the endpoint was disabled, try to restart it after programming descriptor chain prepared by SW earlier, switch SW to fill the other half of chain. Add function dwc2_gadget_fill_isoc_desc() - initializes DMA descriptor for isochronous transfer based on the received request data and endpoint characteristics. Added function dwc2_gadget_start_isoc_ddma() - prepare DMA chain for isochronous transfer in DDMA, programs corresponding DMA address to DEPDMA, enables the endpoint. This function is called once SW decides to start isochronous IN or OUT transfer depend on reception of NAK or OUTTknEPdis interrupts indicating first isochronous token arrival from host. Signed-off-by:
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Vahram Aharonyan authored
In DDMA mode incompISOOUT should be masked, similar as Bulk Out - XferCompl and BNA should be handled. incompISOIN is not valid in DDMA and is not getting asserted. Signed-off-by:
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Vahram Aharonyan authored
Preparing for isochronous transfers support adding in DDMA mode. In DDMA isochronous transfers are handled differently compared to Slave and BDMA modes. This is caused by fact that isoc requests contain data for one frame/microframe. HW descriptor should contain data of one frame/microframe as well. Hence each DMA descriptor in the chain will correspond to one usb request. Decided to divide endpoints descriptor chain to two halves - while one will be processed by HW, other one will be under SW control. First part will be passed to HW once ISOC traffic needs to be started. In parallel to HW's work SW will keep creating new entries in the other half of chain if new requests arrive in ep_queue routine. This will allow passing of already pre-prepared descriptors to HW immediately after endpoint gets disabled. The endpoint should be disabled once HW closes descriptor with "L" bit set. Afterwards SW will switch to use first part of chain if more requests are arriving. Add two members to the dwc2_hsotg_ep structure to be used in isochronous transfers' handling in DDMA mode: -isoc_chain_num - indicates which half of EP descriptor chain can be used by SW to add new queued requests while HW is processing other half. -next_desc - index which points to next not yet programmed descriptor in the half of descriptor chain which is under SW control. Also add initialization of these fields in function dwc2_hsotg_ep_enable(). Signed-off-by:
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Vahram Aharonyan authored
Add DCFG register field macro for descriptor DMA mode and update core initialization routine to set that bit accordingly. Signed-off-by:
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Vahram Aharonyan authored
In DDMA mode of operation IN status phase of control write transfer should start after getting StsPhseRcvd interrupt. This interrupt is issued by HW once host starts to send IN tokens after data stage. Signed-off-by:
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Vahram Aharonyan authored
The StsPhseRcvd interrupt should not be enabled in slave mode. Also move the StsPhsRcvd interrupt checking in the endpoint interrupt handler to the correct order according to the databook. The interrupt itself will be implemented in a later commit. Signed-off-by:
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Vahram Aharonyan authored
Update transfer starting dwc2_hsotg_start_req() routine with call of function dwc2_gadget_config_nonisoc_xfer_ddma() to fill descriptor chain. Add call of dwc2_gadget_get_xfersize_ddma() in dwc2_hsotg_handle_outdone() and dwc2_hsotg_complete_in() interrupt handlers for DDMA mode to get information on transferred data from descriptors instead of DXEPTSIZ. Signed-off-by:
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Vahram Aharonyan authored
Add dwc2_gadget_set_ep0_desc_chain() function to switch between EP0 DDMA chains depend on the stage of control transfer. Include EP0 DDMA chain selection during ep_queue called from dwc2_hsotg_enqueue_setup() for setup stage. Selecting and filling DDMA chain for status phase as well - add calls of dwc2_gadget_set_ep0_desc_chain() and dwc2_gadget_config_nonisoc_xfer_ddma() functions. Signed-off-by:
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John Youn authored
This property was mistakenly added, then removed, so don't read it in. Signed-off-by:
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Nicolae Rosia authored
All users are DT-only and it makes no sense to keep unused code Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
Nicolae Rosia <Nicolae_Rosia@mentor.com> Signed-off-by:
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John Youn authored
Now that all the infrastructure is in place, we can clear events in the top-half handler in order to bring IRQ line low ASAP. This is also a necessary step in order to implement workaround for known erratum in follow-up patches. Signed-off-by:
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John Youn authored
Let's start copying events from evt->buf to evt->cache and use evt->cache for processing events. A follow-up patch will be added to clear events in the top-half handler in order to bring IRQ line low as soon as possible. Signed-off-by:
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