- 31 Oct, 2018 5 commits
-
-
Madhav Chauhan authored
This patch programs maximum size of the payload transmitted from peripheral back to the host processor using short packet as a part of panel programming. v2: Rebase v3 by Jani: - Add FIXME note. Signed-off-by:
Madhav Chauhan <madhav.chauhan@intel.com> Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/ed9df910326adf32eb2bc1cd1a5097d0dda94da8.1540900289.git.jani.nikula@intel.com
-
Madhav Chauhan authored
Move DSI connector functions to intel_dsi.c and make them available to both legacy and ICL DSI. v2 by Jani: - Move the functions to intel_dsi.c - Don't reuse intel_dsi_connector_destroy() Signed-off-by:
-
Madhav Chauhan authored
This patch moves intl_dsi_host_init() code to intel_dsi.c so that legacy and gen11 DSI code can share this code. v2 by Jani: - Move the shared stuff to intel_dsi.c Signed-off-by:
-
Matthew Auld authored
When using softpin it's not enough to just pad the vma size, we also need to ensure the vma offset is at the start of the pt boundary, if we plan to utilize 64K pages. Therefore to improve test coverage we should use both aligned and unaligned gtt offsets in igt_write_huge. Suggested-by:
Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by:
Matthew Auld <matthew.auld@intel.com> Cc: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by:
-
Hang Yuan authored
This reverts commit c9e66688. Checked GVT codes that guest PPGTT PTE flag bits are propagated to shadow PTE. Read/write bit is not changed. Further tested by i915 self-test case "igt_ctx_readonly". No error or GPU hang was detected. So enable read-only support under GVT. Signed-off-by:
Hang Yuan <hang.yuan@linux.intel.com> Acked-by:
Zhenyu Wang <zhenyuw@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/1540883281-11359-1-git-send-email-hang.yuan@linux.intel.comAcked-by:
-
- 30 Oct, 2018 4 commits
-
-
Animesh Manna authored
ICL supports DC5, DC6, and DC9. Enable DC9 during screen-off, and enable DC5/6 when appropriate. v2: (James Ausmus) - Also handle ICL as GEN9_LP in i915_drm_suspend_late and i915_drm_suspend_early - Add DC9 to gen9_dc_mask for ICL - Re-order GEN checks for newest platform first - Use INTEL_GEN instead of INTEL_INFO->gen - Use INTEL_GEN >= 11 instead of IS_ICELAKE - Consolidate GEN checks v3: (James Ausmus) - Also allow DC6 for ICL (Imre, Art) - Simplify !(GEN >= 11) to GEN < 11 (Imre) v4: (James Ausmus) - Don't call intel_power_sequencer_reset after DC9 for Gen11+, as the PPS regs are Always On - Rebase against upstream changes v5: (Anusha Srivatsa) - rebased against the latest upstream changes. v6: (Anusha Srivatsa) - rebased.Use INTEL_GEN consistently. - Simplify the code (Rodrigo) v7: rebased. Change order according to platforms(Jyoti) v8: rebased. Change the check from platform specific to HAS_PCH_SPLIT(). Add comment in code to be more clear.(Rodrigo) Cc: Imre Deak <imre.deak@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
Animesh Manna <animesh.manna@intel.com> Signed-off-by:
James Ausmus <james.ausmus@intel.com> Signed-off-by:
Anusha Srivatsa <anusha.srivatsa@intel.com> Tested-by:
Jyoti Yadav <jyoti.r.yadav@intel.com> Reviewed-by:
Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by:
-
Chris Wilson authored
If we reduce the suspend function for intel_opregion to do the minimum required, the resume function can also do the simple task of notifier the ACPI bios that we are back. This avoid some nasty restrictions on the likes of register_acpi_notifier() that are not allowed during the early phase of resume. v2: Keep the order of acpi notify vs turning off ardy/drdy the same. Signed-off-by:
Imre Deak <imre.deak@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181030110554.4111-1-chris@chris-wilson.co.uk
-
Chris Wilson authored
If we can prevent stray writes from landing in the scratch page, we can reuse the same page and same scratch PT for all contexts without fear of information leaks and side-channels. Signed-off-by:
-
Chris Wilson authored
Record the scratch PTE encoding upon creation rather than recomputing the bits everytime. This is important for the next patch where we forgo having a valid scratch page with which we may compute the bits and so require keeping the PTE value instead. v2: Fix up scrub_64K to use scratch_pte as well. Signed-off-by:
-
- 29 Oct, 2018 15 commits
-
-
Dhinakaran Pandiyan authored
intel_fb_pitch_limit() has the parameters pixel_format and fb_modifier switched in their positions. The parameters are however used correctly, but change the order for consistency. Also use kernel data types for both parameters. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Reviewed-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181026195342.16828-1-dhinakaran.pandiyan@intel.com
-
Dhinakaran Pandiyan authored
The PLANE_AUX_OFFSET mmio does not exist on ICL, do not program it. We'll still calculate the aux offset as it is required for adjusing x-y offsets. Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Signed-off-by:
-
Dhinakaran Pandiyan authored
A framebuffer can comprise surfaces with distinct tiling formats, making checks against modifier alone insufficient. Make use of a function to identify a linear surface based on both modifier and color plane. v2: Typo fix v3: remove 'inline' from function definition (Ville) Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Signed-off-by:
-
Dhinakaran Pandiyan authored
The bits weren't defined in descending order. v2: Move definitions in a separate patch (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by:
Manasi Navare <manasi.d.navare@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181005185643.31660-2-dhinakaran.pandiyan@intel.com
-
Dhinakaran Pandiyan authored
The shifts for VSC_SELECT bits are wrong, fix it. Good thing is the definitions are unused. v2: Moves definitions in another patch (Manasi) Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Fixes: 7af2be6d ("drm/i915/icl: Add VIDEO_DIP registers") Signed-off-by:
-
Rodrigo Vivi authored
The specially case for SKL for not controlled sagv is already taken care inside intel_enable_sagv, so there's no need to duplicate the check here. v2: Go one step further and remove skl special case. (Jani) v3: Separate runtime status handle from has_sagv flag. v4: Go back and accept simple Jani proposed solution. Signed-off-by:
-
Chris Wilson authored
The vm of two contexts are supposed to be independent, such that a stray write by one cannot be detected by another. Normally the GTT is filled explicitly by userspace, but the space in between objects is filled with a scratch page -- and that scratch page should not be able to form an inter-context backchannel. Signed-off-by:
-
Rodrigo Vivi authored
While checking the opportunity to add a display_gen check to allow glk and cnl to be on same bucket I noticed these FIXME cases here. So I got the confirmation from HW architect that we actually never needed this workaround. "GLK supports 2 pixel per clock, so pixel clock can be up to 2 * cdclk." So, this reverts commit 97f55ca5 ("drm/i915/glk: limit pixel clock to 99% of cdclk workaround") Fixes: 97f55ca5 ("drm/i915/glk: limit pixel clock to 99% of cdclk workaround") Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Madhav Chauhan <madhav.chauhan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Cc: Clinton Taylor <clinton.a.taylor@intel.com> Cc: Arthur J Runyan <arthur.j.runyan@intel.com> Signed-off-by:
-
Rodrigo Vivi authored
commit ac657f64 ("drm/i915: Introduce IS_GEN macro") introduced GEN_FOREVER that was never used. My first attempt was to rename it to FOREVER since GEN is already part of the macro. Then I used coccinelle to change all -INTEL_GEN(e1) >= e2 +INTEL_GEN_RANGE(e1, e2, FOREVER) -INTEL_GEN(e1) <= e2 +INTEL_GEN_RANGE(e1, 0, e2) and I liked it. However I didn't like very much the remaining INTEL_GEN(dev_priv) < n and: INTEL_GEN(e1) < n INTEL_GEN_RANGE(e1, 0, n - 1) didn't make much sense either. So INTEL_GEN use for > or < seems a better unified way for unlimited bounds. So, no reason to keep GEN_FOREVER here. Let's kill before someone start using it. v2: Remove remaining GEN_FOREVER forgotten in a comment. (Daniel) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
Daniel Vetter <daniel.vetter@ffwll.ch> Link: https://patchwork.freedesktop.org/patch/msgid/20181026195143.20353-2-rodrigo.vivi@intel.com
-
Rodrigo Vivi authored
Whenever possible we should stick with IS_GEN<n> checks. Bitmaks has been introduced on commit ae7617f0 ("drm/i915: Allow optimized platform checks") for efficiency. Let's stick with it whenever possible. This patch was generated with coccinelle: spatch -sp_file is_gen.cocci *{c,h} --in-place is_gen.cocci: @gen2@ expression e; @@ -INTEL_GEN(e) == 2 +IS_GEN2(e) @gen3@ expression e; @@ -INTEL_GEN(e) == 3 +IS_GEN3(e) @gen4@ expression e; @@ -INTEL_GEN(e) == 4 +IS_GEN4(e) @gen5@ expression e; @@ -INTEL_GEN(e) == 5 +IS_GEN5(e) @gen6@ expression e; @@ -INTEL_GEN(e) == 6 +IS_GEN6(e) @gen7@ expression e; @@ -INTEL_GEN(e) == 7 +IS_GEN7(e) @gen8@ expression e; @@ -INTEL_GEN(e) == 8 +IS_GEN8(e) @gen9@ expression e; @@ -INTEL_GEN(e) == 9 +IS_GEN9(e) @gen10@ expression e; @@ -INTEL_GEN(e) == 10 +IS_GEN10(e) @gen11@ expression e; @@ -INTEL_GEN(e) == 11 +IS_GEN11(e) Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Signed-off-by:
-
Ramalingam C authored
Intel HDCP2.2 registers are defined with addr offsets and bit details. v2: Replaced the arith calc with _PICK [Sean Paul] v3: No changes. v4: %s/HDCP2_CTR_DDI/HDCP2_CTL_DDI [Uma] v5: Added parentheses for the parameters of macro. v6: No changes v7: No changes Signed-off-by:
Ramalingam C <ramalingam.c@intel.com> Reviewed-by:
Sean Paul <seanpaul@chromium.org> Reviewed-by:
Uma Shankar <uma.shankar@intel.com> Signed-off-by:
-
Ramalingam C authored
This patch adds HDCP register definitions for HDMI and DP HDCP adaptations. HDMI specific HDCP2.2 register definitions are added into drm_hdcp.h, where as HDCP2.2 register offsets in DPCD offsets are defined at drm_dp_helper.h. v2: bit_field definitions are replaced by macros. [Tomas and Jani] v3: No Changes. v4: Comments style and typos are fixed [Uma] v5: Fix for macros. v6: Adds _MS to the timeouts to represent units [Sean Paul] v7: Macro DP_HDCP_2_2_REG_EKH_KM_OFFSET renamed [Uma] Redundant macro is removed [Uma] Signed-off-by:
-
Ramalingam C authored
This patch defines the hdcp2.2 protocol messages for authentication. v2: bit_fields are removed. Instead bitmasking used. [Tomas and Jani] prefix HDCP_2_2_ is added to the macros. [Tomas] v3: No Changes. v4: Style and spellings are fixed [Uma] v5: Fix for macros. v6: comment for Type is improved [Sean Paul] v7: %s/HDCP_2_2_LPRIME_HALF_LEN/HDCP_2_2_V_PRIME_HALF_LEN [Uma] %s/uintxx_t/uxx v8: %s/eceiver_id/receiver_id Signed-off-by:
-
Ramalingam C authored
As a policy, this change considers all I915 programming failures and HW failures as ERRORS. Where as all HDCP failures due to the sink is considered as DEBUG logs. Signed-off-by:
-
Ramalingam C authored
Considering significant number of HDCP specific variables, it will be clean to have separate struct for HDCP. New structure called intel_hdcp is added within intel_connector. v2: struct hdcp statically allocated. [Sean Paul] enable and disable function parameters are retained.[Sean Paul] v3: No Changes. v4: Commit msg is rephrased [Uma] v5: Comment for mutex definition. v6: hdcp_ prefix from all intel_hdcp members are removed [Sean Paul] inline function intel_hdcp_to_connector is defined [Sean Paul] v7: %s/uint64_t/u64 v8: Rebased Signed-off-by:
-
- 26 Oct, 2018 6 commits
-
-
Chris Wilson authored
A danger encountered when resetting the seqno (using debugfs/i915_next_seqno) is that as we change the breadcrumb stored in the HWSP, it may be inspected by the signaler thread leading to confusion in our sanity checks. <0> [136.331342] i915/sig-347 3..s1 136336154us : execlists_submission_tasklet: rcs0 awake?=1, active=5 <0> [136.331373] i915/sig-347 3d.s2 136336155us : process_csb: rcs0 cs-irq head=5, tail=0 <0> [136.331402] i915/sig-347 3d.s2 136336155us : process_csb: rcs0 csb[0]: status=0x00000018:0x00000002, active=0x5 <0> [136.331434] i915/sig-347 3d.s2 136336156us : process_csb: rcs0 out[0]: ctx=2.1, global=219 (fence 46:8455) (current 219), prio=0 <0> [136.331466] i915/sig-347 3d.s2 136336156us : process_csb: rcs0 completed ctx=2 <0> [136.332027] gem_exec-1049 0.... 136336246us : reset_all_global_seqno.part.5: rcs0 seqno 219 (current 219) -> -43 <0> [136.332056] gem_exec-1049 0.... 136336251us : reset_all_global_seqno.part.5: bcs0 seqno 183 (current 183) -> -43 <0> [136.332085] gem_exec-1049 0.... 136336255us : reset_all_global_seqno.part.5: vcs0 seqno 191 (current 191) -> -43 <0> [136.332114] gem_exec-1049 0.... 136336259us : reset_all_global_seqno.part.5: vcs1 seqno 180 (current 180) -> -43 <0> [136.332143] gem_exec-1049 0.... 136336262us : reset_all_global_seqno.part.5: vecs0 seqno 212 (current 212) -> -43 <0> [136.332174] i915/sig-347 3.... 136336280us : intel_breadcrumbs_signaler: intel_breadcrumbs_signaler:673 GEM_BUG_ON(!i915_request_completed(rq)) Signed-off-by:
Tvrtko Ursulin <tvrtko.ursulin@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181024104939.2861-1-chris@chris-wilson.co.uk
-
Chris Wilson authored
Use the live_test struct to record the reset count before and compare it at the end of the test to assert that no mystery hang occurred during the test. v2: Check per-engine resets as well Signed-off-by:
-
Tvrtko Ursulin authored
Upcoming GuC code will need to read the fused off engine masks as well, and will also want to have them as enabled instead of disabled masks. To consolidate the read-out place we can store them in this fashion inside INTEL_INFO so they can be easily referenced in the future. Signed-off-by:
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181018104106.30147-1-tvrtko.ursulin@linux.intel.com
-
Chris Wilson authored
Beware mixing unsigned long constants and 64b values, as on 32b the constant will be zero extended and discard the high 32b when used as a mask! Reported-by:
Sergii Romantsov <sergii.romantsov@globallogic.com> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108282Signed-off-by:
-
Chris Wilson authored
Since we use a 64b virtual GTT irrespective of the system, we want to ensure that the GTT computations remains 64b even on 32b systems, including treatment of huge virtual pages. No code generation changes on 64b: Reported-by:
-
Clint Taylor authored
HDMI 2.0 594Mhz modes were incorrectly selecting 25.200Mhz Automatic N value mode instead of HDMI specification values. V2: Fix 88.2 Hz N value Cc: Jani Nikula <jani.nikula@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by:
Clint Taylor <clinton.a.taylor@intel.com> Signed-off-by:
-
- 25 Oct, 2018 1 commit
-
-
Imre Deak authored
In order to ensure that our system suspend and resume callbacks are called in the correct order wrt. those of the HDA driver add a device link to the HDA driver during audio component binding time. With i915 as the supplier and HDA as the consumer the PM framework will guarantee the HDA->i915 suspend (and shutdown) and i915->HDA resume order. Atm, the lack of this ordering is not a problem, since all the i915 suspend/resume steps that need to be ordered wrt. the HDA driver's suspend/resume steps are separated out to the i915 suspend_late/resume_early hooks. That will change in a follow-up patchset where we'll need this ordering guarantee for steps that are in the i915 suspend/resume hooks (and which can't be moved to suspend_late/resume_early for other reasons). So this patch is a preparation for that follow-up patchset. The change also allows us to move towards removing the i915 suspend_late/resume_early hooks alltogether. Since we only need to ensure the ordering during suspend/resume and not during driver probing create the link with DL_FLAG_STATELESS. Since the probe time ordering has to be optional we use the component framework for that. Similarly for runtime PM we depend on the audio driver getting/putting an i915 runtime PM reference whenever it needs it (along with the proper i915 display power domain) via the audio component ops get_power / put_power hooks. So we create the device link without DL_FLAG_PM_RUNTIME. v2: (Ville) - Add a note to the commit message about not using the device link runtime PM ordering. - Handle the error return from device_link_add(). Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Takashi Iwai <tiwai@suse.de> Cc: Lukas Wunner <lukas@wunner.de> Signed-off-by:
-
- 24 Oct, 2018 9 commits
-
-
Chris Wilson authored
make W=1 caught the implicit prototypes (as would sparse): drivers/gpu/drm/i915/intel_sprite.c:462:1: error: no previous prototype for ‘skl_update_plane’ [-Werror=missing-prototypes] skl_update_plane(struct intel_plane *plane, ^~~~~~~~~~~~~~~~ drivers/gpu/drm/i915/intel_sprite.c:487:1: error: no previous prototype for ‘skl_disable_plane’ [-Werror=missing-prototypes] skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc) ^~~~~~~~~~~~~~~~~ Fixes: 1e364f90 ("drm/i915/gen11: Program the Y and UV plane for planar mode correctly, v3.") Signed-off-by:
Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181024105402.18915-1-chris@chris-wilson.co.uk
-
Lionel Landwerlin authored
Forgot to add the description of this option in a previous commit. Signed-off-by:
Lionel Landwerlin <lionel.g.landwerlin@intel.com> Fixes: cd956bfc ("drm/i915/perf: add a parameter to control the size of OA buffer") Reviewed-by:
-
Ville Syrjälä authored
The 16Gb DIMM w/a is not applicable to BXT or GLK. Limit it to the appropriate platforms. This was especially harsh on GLK since we don't even try to read the DIMM information on that platforms, hence valid_dimm was always false and thus we always tried to apply the w/a. Furthermore the w/a pushed the level 0 latency above the level 1 latency, which doesn't really make sense. v2: Do the check when populating is_16gb_dimm (Mahesh) Cc: Mahesh Kumar <mahesh1.kumar@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Fixes: 86b59287 ("drm/i915: Implement 16GB dimm wa for latency level-0") Signed-off-by:
Mahesh Kumar <mahesh1.sh.kumar@gmail.com>
-
Maarten Lankhorst authored
Now that we implemented support for planar formats on gen11, we can finally advertise it. Changes since v1: - Re-add change to skl_plane_has_planar(), was lost in rebase noise. Signed-off-by:
-
Maarten Lankhorst authored
The UV plane is the master plane that does all color correction etc. It needs to be programmed with the dimensions for color plane 1 (UV). The Y plane just feeds the Y pixels to it. Program the scaler from the master only, and set PLANE_CTL_YUV420_Y_PLANE on the slave plane. Changes since v1: - Make a common skl_program_plane, and use it for both plane updates. Changes since v2: - Make color_plane explicit, to clarify skl_update_plane(). (Ville) Signed-off-by:
-
Maarten Lankhorst authored
We configure the chroma upsampler with the same chroma siting as used by the scaler for consistency, the chroma upsampler is used instead of the scaler for YUV 4:2:0 on ICL's HDR planes. Signed-off-by:
-
Maarten Lankhorst authored
The first 3 planes (primary, sprite 0 and 1) have a dedicated chroma upsampler to upscale YUV420 to YUV444 and the scaler should only be used for upscaling. Because of this we shouldn't program the scalers in planar mode if NV12 and the chroma upsampler are used. Instead program the scalers like on normal planes. Sprite 2 and 3 have no dedicated scaler, and need to program the selected Y plane in the scaler mode. Changes since v1: - Make the comment less confusing. Changes since v2: - Fix checkpatch warning (Matt) - gen10- -> Pre-gen11 (Ville) - PS_SCALER_MODE_PACKED -> PS_SCALER_MODE_NORMAL. (Matt) - Add comment about scaler mode in intel_atomic_setup_scaler(). (Matt) - Rename need_scaling to need_scaler. (Matt) - Move the crtc need_scaling check to skl_update_scaler_crtc(). Signed-off-by:
-
Maarten Lankhorst authored
Skylake style watermarks program the UV parameters into wm->uv_wm, and have a separate DDB allocation for UV blocks into the same plane. Gen11 watermarks have a separate plane for Y and UV, with separate mechanisms. The simplest way to make it work is to keep the current way of programming watermarks and calculate the Y and UV plane watermarks from the master plane. Changes since v1: - Constify crtc_state where possible. - Make separate paths for planar formats in skl_build_pipe_wm() (Matt) - Make separate paths for calculating total data rate. (Matt) - Make sure UV watermarks are unused on gen11+ by adding a WARN. (Matt) Signed-off-by:
-
Maarten Lankhorst authored
To make NV12 working on icl, we need to update 2 planes simultaneously. I've chosen to do this in the CRTC step after plane validation is done, so we know what planes are (in)visible. The linked Y plane will get updated in intel_plane_update_planes_on_crtc(), by the call to update_slave, which gets the master's plane_state as argument. The link requires both planes for atomic_update to work, so make sure skl_ddb_add_affected_planes() adds both states. Changes since v1: - Introduce icl_is_nv12_y_plane(), instead of hardcoding sprite numbers. - Put all the state updating login in intel_plane_atomic_check_with_state(). - Clean up changes in intel_plane_atomic_check(). Changes since v2: - Fix intel_atomic_get_old_plane_state() to actually return old state. - Move visibility changes to preparation patch. - Only try to find a Y plane on gen11, earlier platforms only require a single plane. Changes since v3: - Fix checkpatch warning about to_intel_crtc() usage. - Add affected planes from icl_add_linked_planes() before check_planes(), it's a cleaner way to do this. (Ville) Changes since v4: - Clear plane links in icl_check_nv12_planes() for clarity. - Only pass crtc_state to icl_check_nv12_planes(). - Use for_each_new_intel_plane_in_state() in icl_check_nv12_planes. - Rename aux to linked. (Ville) Signed-off-by:
-
