- 09 Jan, 2008 4 commits
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Stephen Neuendorffer authored
Missed this one in the boot loader before. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Stephen Neuendorffer authored
This now better describes what the UBoot device tree generator actually does. In particular: 1) Nodes have a label derived from the device name, and a node name derived from a generic version of the device type, e.g. 'ethernet', 'serial', etc. 2) Usage of compound nodes (representing more than one device in the same IP) which actually works. This requires having a valid compatible node, and all the other things that a bus normally has. I've chosen 'xlnx,compound' as the bus name to describe these compound nodes. In addition, I've clarified some of the language relating to how mhs nodes should be represent in the device tree. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Stephen Neuendorffer authored
Includes both flavors of plb, opb, dcr, and a pseudo 'compound' bus for representing compound peripherals containing more than one logical device. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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Stephen Neuendorffer authored
These values now match what is generated by the uboot BSP generator. Signed-off-by: Stephen Neuendorffer <stephen.neuendorffer@xilinx.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
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- 31 Dec, 2007 1 commit
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- 30 Dec, 2007 1 commit
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Paul Mackerras authored
This reverts commit 553aa765 at Ben H's request, because it confused IORESOURCE_* flags with command register bits. Requested-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Paul Mackerras <paulus@samba.org>
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- 28 Dec, 2007 3 commits
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Olof Johansson authored
Enable MSI now that we have an implementation, and enable CONFIG_MD and the raid options by default as well. Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
By default the OpenPIC on PWRficient will bias to one core (since that will improve changes of the other core being able to stay idle/powered down). However, this conflicts with most irq load balancing schemes, since setting an interrupt to be delivered to either core doesn't really result in the load being shared. It also doesn't work well with the soft irq disable feature of PPC, since EE will stay on until the first interrupt is taken while soft disabled. Set the gconf0 config bit that enables even distribution of interrupts among the two cores. Signed-off-by: Olof Johansson <olof@lixom.net>
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Olof Johansson authored
Some PWRficient-based boards have a NMI button that's wired up to a GPIO as interrupt source. By configuring the openpic accordingly, these get delivered as a machine check with high priority, instead of as an external interrupt. The device tree contains a property "nmi-source" in the openpic node for these systems, and it's the (hwirq) source for the input. Also, for these interrupts, the IACK is read from another register than the regular (MCACK instead), but they are EOI'd as usual. So implement said function for the mpic driver. Finally, move a couple of external function defines to include/ instead of local under sysdev. Being able to mask/unmask and eoi directly saves us from setting up a dummy irq handler that will never be called. Signed-off-by: Olof Johansson <olof@lixom.net>
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- 25 Dec, 2007 2 commits
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Josh Boyer authored
Update the 4xx board defconfigs Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Remove some unneeded braces and make a busy loop more obvious. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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- 24 Dec, 2007 4 commits
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Josh Boyer authored
Some machine_xx_initcall macros were recently added that check for the machine type before calling the function. This converts the 4xx platforms to use those for bus probing. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Remove the declarations for isa_io_base and isa_mem_base as they are declared in pci-common.c now. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
The e200 and e500 platforms are separated in various parts of the kernel with ifdefs, most notably reg_booke.h and traps.c. The new machine_check rework requires them to be similarly separated in cputable.c to avoid compile errors. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Mark the of_device_id structures used to probe the various busses on 4xx as __initdata. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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- 23 Dec, 2007 25 commits
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Josh Boyer authored
Enable PCI support for these eval boards among other things. Also selects PCI for Rainier in the Kconfig file. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
This patch adds basic support for the AMCC Makalu board to arch/powerpc. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Currently we have some limitations in the 4xx PCIe driver and can't support all possible PCIe busses. But the current limits in the dts file are quite low (only 16 busses per RC). This patch increases the number to 64 per RC. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
This adds PCI entry to PowerPC 440GRx Rainier DTS. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
Renaming the CPU nodes with generic names put the CPU model in the "model" property and thus broke the PowerPC 440EP(x)/440GR(x) identical PVR workaround. The updates it to use the new model property for CPU identification. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Recent DTC versions disallow certain special characters in full paths without being quoted with {}. That however breaks compatibility with older DTC versions. Work around this by renaming the CPU nodes for the 4xx files to a generic node name, and specify the processor type in the model property of the CPU node. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
This patch sets the ibpre flag (Inbound Presence) for the 405EX in the 4xx PCIe driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
The recent changes from Benjamin Herrenschmidt to the ibm_newemac now make it possible to support other 4xx variants by just defining the correct properties in the device tree. In this case of the 405EX we need to define "has-mdio" in the RGMII node and "has-inverted-stacr-oc" and "has-new-stacr-staopc" in the EMAC node same as on the 440EPx. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
For EMAC support, 405EX needs to be defined to enable the corresponding EMAC features (IBM_NEW_EMAC_EMAC4, etc.). Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Stefan Roese authored
Right now TLB entry 0 ist used as UART0 mapping for the early debug output (via CONFIG_SERIAL_TEXT_DEBUG). This causes problems when many TLB's get used upon Linux bootup (e.g. while PCIe scanning behind bridges and/or switches on 440SPe platforms). This will overwrite the TLB 0 entry and further debug output's may crash/hang the system. This patch moves the early debug UART0 TLB entry from 0 to 62 as done in arch/powerpc. This way it is in the "pinned" area and will not get overwritten. Also the arch/ppc/mm/44x_mmu.c code is now synced with the newer code from arch/powerpc. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
Update the Rainier wrapper for the libfdt merge and add the pci flags to the platform file. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
A small error caused a header file to be removed making sequoia support no longer compile. Fix it. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
PowerPC 440Epx/GRx Sequoia/Rainier updates for 2.6.25 Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Josh Boyer authored
The mechanism to do the setup for 440A cores changed recently. This fixes the 440grx setup function to call __fixup_440A_mcheck. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
This adds PCI entry to PowerPC 440EPx Sequoia DTS. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
Correct the PowerPC 440GRx machine check callback. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
This is a UIC cascade handler rework to use set_irq_chained_handler() for cascade, just like othe ppc platforms do. With current implementation we have additional redirection for irq handler and we call generic_handle_irq twice (once for the primary uic and the other time for handling cascade interrupt). This causes Ingo's realtime support patch to stop working on 4xx. Not sure of any other possible problems though, but with set_irq_chained_handler() we can abolish "struct irqaction cascade" from the chip descriptor and call generic_handle_irq() once, directly for cascade irq. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
This patch makes PowerPC 4xx UIC use generic level irq handler instead of a custom handle_uic_irq() function. We ack only edge irqs in mask_ack callback, since acking a level irq on UIC has no effect if the interrupt is still asserted by the device, even if the interrupt is already masked. So, to really de-assert the interrupt we need to de-assert the external source first *and* ack it on UIC then. The handle_level_irq() function masks and ack's the interrupt with mask_ack callback prior to calling the actual ISR and unmasks it at the end. So, to use it with UIC interrupts we need to ack level irqs in the unmask callback instead, after the ISR has de-asserted the external interrupt source. Even if we ack the interrupt that we didn't handle (unmask/ack it at the end of the handler, while next irq is already pending) it will not de-assert the irq, untill we de-assert its exteral source. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
PowerPC 440GRx Rainier default config. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
PowerPC 440GRx Rainier board support. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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Valentine Barshak authored
PowerPC 440GRx Rainier DTS. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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