- 26 May, 2020 1 commit
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Mark Brown authored
Originally spi_write_then_read() used a fixed statically allocated buffer which limited the maximum message size it could handle. This restriction was removed a while ago so that we could dynamically allocate a buffer if required but the kerneldoc was not updated to reflect this, do so. Reported-by:
Marc Kleine-Budde <mkl@pengutronix.de> Signed-off-by:
Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20200525133120.57273-1-broonie@kernel.orgSigned-off-by:
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- 25 May, 2020 2 commits
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dillon min authored
spi: flags 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' can't be coexit with 'SPI_3WIRE' mode since chip spi driver need get the transfer direction by 'tx_buf' and 'rx_buf' of 'struct spi_transfer' in 'SPI_3WIRE' mode. so, we need bypass 'SPI_CONTROLLER_MUST_RX' and 'SPI_CONTROLLER_MUST_TX' feature in 'SPI_3WIRE' mode Signed-off-by:
dillon min <dillon.minfei@gmail.com> Link: https://lore.kernel.org/r/1590378348-8115-9-git-send-email-dillon.minfei@gmail.comSigned-off-by:
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dillon min authored
in l3gd20 driver startup, there is a setup failed error return from stm32 spi driver " [ 2.687630] st-gyro-spi spi0.0: supply vdd not found, using dummy regulator [ 2.696869] st-gyro-spi spi0.0: supply vddio not found, using dummy regulator [ 2.706707] spi_stm32 40015000.spi: SPI transfer setup failed [ 2.713741] st-gyro-spi spi0.0: SPI transfer failed: -22 [ 2.721096] spi_master spi0: failed to transfer one message from queue [ 2.729268] iio iio:device0: failed to read Who-Am-I register. [ 2.737504] st-gyro-spi: probe of spi0.0 failed with error -22 " after debug into spi-stm32 driver, st-gyro-spi split two steps to read l3gd20 id first: send command to l3gd20 with read id command in tx_buf, rx_buf is null. second: read id with tx_buf is null, rx_buf not null. so, for second step, stm32 driver recongise this process as 'SPI_SIMPLE_RX' from stm32_spi_communication_type(), but there is no related process for this type in stm32f4_spi_set_mode(), then we get error from stm32_spi_transfer_one_setup(). we can use two method to fix this bug. 1, use stm32 spi's "In unidirectional receive-only mode (BIDIMODE=0 and RXONLY=1)". but as our code running in sdram, the read latency is too large to get so many receive overrun error in interrupts handler. 2, use stm32 spi's "In full-duplex (BIDIMODE=0 and RXONLY=0)", as tx_buf is null, so add flag 'SPI_MASTER_MUST_TX' to spi master. Change since V4: 1 remove dummy data sent out by stm32 spi driver 2 add flag 'SPI_MASTER_MUST_TX' to spi master Signed-off-by:
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- 22 May, 2020 9 commits
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Mark Brown authored
If the delay used is long enough the spi_delay_exec() will use a sleeping function to implement it. Add a might_sleep() here to help avoid callers using this from an atomic context and running into problems at runtime on other systems. Suggested-by:
Serge Semin <Sergey.Semin@baikalelectronics.ru> Signed-off-by:
Andy Shevchenko <andriy.shevchenko@linux.intel.com> Link: https://lore.kernel.org/r/20200522155005.46099-1-broonie@kernel.orgSigned-off-by:
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Mark Brown authored
Merge series "spi: dw: Add generic DW DMA controller support" from Serge Semin <Sergey.Semin@baikalelectronics.ru>: Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW APB SSI devices embedded into the SoC. Currently the DMA-based transfers are supported by the DW APB SPI driver only as a middle layer code for Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal platform DMAC device we introduced a set of patches to fix it within this series. First of all we need to add the Tx and Rx DMA channels support into the DW APB SSI binding. Then there are several fixes and cleanups provided as a initial preparation for the Generic DMA support integration: add Tx/Rx finish wait methods, clear DMAC register when done or stopped, Fix native CS being unset, enable interrupts in accordance with DMA xfer mode, discard static DW DMA slave structures, discard unused void priv pointer and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst length parametrisation and make sure it's optionally set in accordance with the DMA max-burst capability. In order to have the DW APB SSI MMIO driver working with DMA we need to initialize the paddr field with the physical base address of the DW APB SSI registers space. Then we unpin the Intel MID specific code from the generic DMA one and placed it into the spi-dw-pci.c driver, which is a better place for it anyway. After that the naming cleanups are performed since the code is going to be used for a generic DMAC device. Finally the Generic DMA initialization can be added to the generic version of the DW APB SSI IP. Last but not least we traditionally convert the legacy plain text-based dt-binding file with yaml-based one and as a cherry on a cake replace the manually written DebugFS registers read method with a ready-to-use for the same purpose regset32 DebugFS interface usage. This patchset is rebased and tested on the spi/for-next (5.7-rc5): base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next") Link: https://lore.kernel.org/linux-spi/20200508132943.9826-1-Sergey.Semin@baikalelectronics.ru/ Changelog v2: - Rebase on top of the spi repository for-next branch. - Move bindings conversion patch to the tail of the series. - Move fixes to the head of the series. - Apply as many changes as possible to be applied the Generic DMA functionality support is added and the spi-dw-mid is moved to the spi-dw-dma driver. - Discard patch "spi: dw: Fix dma_slave_config used partly uninitialized" since the problem has already been fixed. - Add new patch "spi: dw: Discard unused void priv pointer". - Add new patch "spi: dw: Discard dma_width member of the dw_spi structure". n_bytes member of the DW SPI data can be used instead. - Build the DMA functionality into the DW APB SSI core if required instead of creating a separate kernel module. - Use conditional statement instead of the ternary operator in the ref clock getter. Link: https://lore.kernel.org/linux-spi/20200515104758.6934-1-Sergey.Semin@baikalelectronics.ru/ Changelog v3: - Use spi_delay_exec() method to wait for the DMA operation completion. - Explicitly initialize the dw_dma_slave members on stack. - Discard the dws->fifo_len utilization in the Tx FIFO DMA threshold setting from the patch where we just add the default burst length constants. - Use min() method to calculate the optimal burst values. - Add new patch which moves the spi-dw.c source file to spi-dw-core.c in order to preserve the DW APB SSI core driver name. - Add commas in the debugfs_reg32 structure initializer and after the last entry of the dw_spi_dbgfs_regs array. Link: https://lore.kernel.org/linux-spi/20200521012206.14472-1-Sergey.Semin@baikalelectronics.ru Changelog v4: - Get back ndelay() method to wait for an SPI transfer completion. spi_delay_exec() isn't suitable for the atomic context. Co-developed-by:Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru> Signed-off-by:
Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru> Signed-off-by:
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Christopher Hill authored
This patch adds the correcsponding MikroTik vendor and device tree documentation Signed-off-by:
Christopher Hill <ch6574@gmail.com> Link: https://lore.kernel.org/r/20200521183631.37806-3-ch6574@gmail.comSigned-off-by:
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Christopher Hill authored
This patch updates the spi driver spi-rb4xx.c to be device tree aware Signed-off-by:
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Christopher Hill authored
This patch fixes a null pointer bug in the spi driver spi-rb4xx.c by moving the private data initialization to earlier in probe Signed-off-by:
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Serge Semin authored
This member has exactly the same value as n_bytes of the DW SPI private data object, it's calculated at the same point of the transfer method, n_bytes isn't changed during the whole transfer, and they even serve for the same purpose - keep number of bytes per transfer word, though the dma_width is used only to calculate the DMA source/destination addresses width, which n_bytes could be also utilized for. Taking all of these into account let's replace the dma_width member usage with n_bytes one and remove the former. Signed-off-by:
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Serge Semin authored
Seeing the "void *priv" member of the dw_spi data structure is unused let's remove it. The glue-layers can embed the DW APB SSI controller descriptor into their private data object. MMIO driver for instance already utilizes that design pattern. Signed-off-by:
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Serge Semin authored
Having them declared is redundant since each struct dw_dma_chan has the same structure embedded and the structure from the passed dma_chan private pointer will be copied there as a result of the next calls chain: dma_request_channel() -> find_candidate() -> dma_chan_get() -> device_alloc_chan_resources() = dwc_alloc_chan_resources() -> dw_dma_filter(). So just remove the static dw_dma_chan structures and use a locally declared data instance with dst_id/src_id set to the same values as the static copies used to have. Co-developed-by:
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Serge Semin authored
It's pointless to track the Tx overrun interrupts if Rx-only SPI transfer is issued. Similarly there is no need in handling the Rx overrun/underrun interrupts if Tx-only SPI transfer is executed. So lets unmask the interrupts only if corresponding SPI transactions are implied. Co-developed-by:
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- 20 May, 2020 5 commits
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Lukas Wunner authored
On unbind of the BCM2835 SPI driver, the SPI controller is disabled first and the DMA channels are terminated and torn down afterwards. This seems backwards: In the theoretical case that DMA is active, it might try to fill the SPI FIFOs even after the controller has been disabled. Reverse the order, thereby mirroring what's done on ->probe(). Signed-off-by:
Lukas Wunner <lukas@wunner.de> Link: https://lore.kernel.org/r/ac79f1e3d6fd9a1f5e0cb4008c43b98ea70be3c2.1589557526.git.lukas@wunner.deSigned-off-by:
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Lukas Wunner authored
The BCM2835aux SPI driver uses devm_spi_register_master() on bind. As a consequence, on unbind, __device_release_driver() first invokes bcm2835aux_spi_remove() before unregistering the SPI controller via devres_release_all(). This order is incorrect: bcm2835aux_spi_remove() turns off the SPI controller, including its interrupts and clock. The SPI controller is thus no longer usable. When the SPI controller is subsequently unregistered, it unbinds all its slave devices. If their drivers need to access the SPI bus, e.g. to quiesce their interrupts, unbinding will fail. As a rule, devm_spi_register_master() must not be used if the ->remove() hook performs teardown steps which shall be performed after unbinding of slaves. Fix by using the non-devm variant spi_register_master(). Note that the struct spi_master as well as the driver-private data are not freed until after bcm2835aux_spi_remove() has finished, so accessing them is safe. Fixes: 1ea29b39 ("spi: bcm2835aux: add bcm2835 auxiliary spi device driver") Signed-off-by:
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Lukas Wunner authored
The BCM2835 SPI driver uses devm_spi_register_controller() on bind. As a consequence, on unbind, __device_release_driver() first invokes bcm2835_spi_remove() before unregistering the SPI controller via devres_release_all(). This order is incorrect: bcm2835_spi_remove() tears down the DMA channels and turns off the SPI controller, including its interrupts and clock. The SPI controller is thus no longer usable. When the SPI controller is subsequently unregistered, it unbinds all its slave devices. If their drivers need to access the SPI bus, e.g. to quiesce their interrupts, unbinding will fail. As a rule, devm_spi_register_controller() must not be used if the ->remove() hook performs teardown steps which shall be performed after unbinding of slaves. Fix by using the non-devm variant spi_register_controller(). Note that the struct spi_controller as well as the driver-private data are not freed until after bcm2835_spi_remove() has finished, so accessing them is safe. Fixes: 247263db ("spi: bcm2835: use devm_spi_register_master()") Signed-off-by:
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Lukas Wunner authored
When an SPI controller unregisters, it unbinds all its slave devices. For this, their drivers may need to access the SPI bus, e.g. to quiesce interrupts. However since commit ffbbdd21 ("spi: create a message queueing infrastructure"), spi_destroy_queue() is executed before unbinding the slaves. It sets ctlr->running = false, thereby preventing SPI bus access and causing unbinding of slave devices to fail. Fix by unbinding slaves before calling spi_destroy_queue(). Fixes: ffbbdd21 ("spi: create a message queueing infrastructure") Signed-off-by:
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- 19 May, 2020 1 commit
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Kangmin Park authored
Fix unit address to match the first address specified in the reg property of the node in example. Signed-off-by:
Kangmin Park <l4stpr0gr4m@gmail.com> Link: https://lore.kernel.org/r/1589873541-5587-1-git-send-email-l4stpr0gr4m@gmail.comSigned-off-by:
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- 15 May, 2020 8 commits
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Serge Semin authored
Since commit 22d48ad7 ("spi: dw: Add Elkhart Lake PSE DMA support") the spi-dw-mid.c module supports a platform DMA engine handling the DW APB SSI controller requests. Lets alter the DW SPI bindings file to accept the Rx and Tx DMA line specifiers. Signed-off-by:
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Mark Brown authored
Merge series "spi: dw: Add generic DW DMA controller support" from Serge Semin <Sergey.Semin@baikalelectronics.ru>: Baikal-T1 SoC provides a DW DMA controller to perform low-speed peripherals Mem-to-Dev and Dev-to-Mem transaction. This is also applicable to the DW APB SSI devices embedded into the SoC. Currently the DMA-based transfers are supported by the DW APB SPI driver only as a middle layer code for Intel MID/Elkhart PCI devices. Seeing the same code can be used for normal platform DMAC device we introduced a set of patches to fix it within this series. First of all we need to add the Tx and Rx DMA channels support into the DW APB SSI binding. Then there are several fixes and cleanups provided as a initial preparation for the Generic DMA support integration: add Tx/Rx finish wait methods, clear DMAC register when done or stopped, Fix native CS being unset, enable interrupts in accordance with DMA xfer mode, discard static DW DMA slave structures, discard unused void priv pointer and dma_width member of the dw_spi structure, provide the DMA Tx/Rx burst length parametrisation and make sure it's optionally set in accordance with the DMA max-burst capability. In order to have the DW APB SSI MMIO driver working with DMA we need to initialize the paddr field with the physical base address of the DW APB SSI registers space. Then we unpin the Intel MID specific code from the generic DMA one and placed it into the spi-dw-pci.c driver, which is a better place for it anyway. After that the naming cleanups are performed since the code is going to be used for a generic DMAC device. Finally the Generic DMA initialization can be added to the generic version of the DW APB SSI IP. Last but not least we traditionally convert the legacy plain text-based dt-binding file with yaml-based one and as a cherry on a cake replace the manually written DebugFS registers read method with a ready-to-use for the same purpose regset32 DebugFS interface usage. This patchset is rebased and tested on the spi/for-next (5.7-rc5): base-commit: fe9fce6b2cf3 ("Merge remote-tracking branch 'spi/for-5.8' into spi-next") Co-developed-by: -
Chris Ruehl authored
The original implementation set num_chipselect to ROCKCHIP_SPI_MAX_CS_NUM (2) which seems wrong here. spi0 has 2 native cs, all others just one. With enable and use of cs_gpiods / GPIO CS, its correct to set the num_chipselect from the num-cs property and set max_native_cs with the define. If num-cs is missing the default set to num_chipselect = 1. Signed-off-by:
Chris Ruehl <chris.ruehl@gtsys.com.hk> Link: https://lore.kernel.org/r/20200511083022.23678-4-chris.ruehl@gtsys.com.hkSigned-off-by:
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Chris Ruehl authored
Add support for spi slave mode in spi-rockchip. The register map has an entry for it. If spi-slave is set in dts, set this corresponding bit and add to mode_bits the SPI_NO_CS, allow slave mode without explicit CS use. Slave abort function had been added. Signed-off-by:
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Chris Ruehl authored
Cleanup, move from the compatibily layer struct spi_master over to struct spi_controller, and rename the related function calls. Signed-off-by:
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Serge Semin authored
If DMAC register is left uncleared any further DMAless transfers may cause the DMAC hardware handshaking interface getting activated. So the next DMA-based Rx/Tx transaction will be started right after the dma_async_issue_pending() method is invoked even if no DMATDLR/DMARDLR conditions are met. This at the same time may cause the Tx/Rx FIFO buffers underrun/overrun. In order to fix this we must clear DMAC register after a current DMA-based transaction is finished. Co-developed-by:
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Serge Semin authored
This field is used only for the DW SPI DMA code initialization, that's why there were no problems with it being uninitialized in Dw SPI MMIO driver. Since in a further patch we are going to introduce the DW SPI DMA support in the MMIO version of the driver, lets set the field with the physical address of the DW SPI controller registers region. Co-developed-by:
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Serge Semin authored
Commit 6e0a32d6 ("spi: dw: Fix default polarity of native chipselect") attempted to fix the problem when GPIO active-high chip-select is utilized to communicate with some SPI slave. It fixed the problem, but broke the normal native CS support. At the same time the reversion commit ada9e3fc ("spi: dw: Correct handling of native chipselect") didn't solve the problem either, since it just inverted the set_cs() polarity perception without taking into account that CS-high might be applicable. Here is what is done to finally fix the problem. DW SPI controller demands any native CS being set in order to proceed with data transfer. So in order to activate the SPI communications we must set any bit in the Slave Select DW SPI controller register no matter whether the platform requests the GPIO- or native CS. Preferably it should be the bit corresponding to the SPI slave CS number. But currently the dw_spi_set_cs() method activates the chip-select only if the second argument is false. Since the second argument of the set_cs callback is expected to be a boolean with "is-high" semantics (actual chip-select pin state value), the bit in the DW SPI Slave Select register will be set only if SPI core requests the driver to set the CS in the low state. So this will work for active-low GPIO-based CS case, and won't work for active-high CS setting the bit when SPI core actually needs to deactivate the CS. This commit fixes the problem for all described cases. So no matter whether an SPI slave needs GPIO- or native-based CS with active-high or low signal the corresponding bit will be set in SER. Signed-off-by:
Charles Keepax <ckeepax@opensource.cirrus.com> Reviewed-by:
Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20200515104758.6934-5-Sergey.Semin@baikalelectronics.ruSigned-off-by:
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- 12 May, 2020 2 commits
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Andy Shevchenko authored
devm_platform_ioremap_resource() will issue a message in the error case. Thus, no need to duplicate in the driver. Signed-off-by:
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Kunihiko Hayashi authored
Convert UniPhier SPI controller binding to DT schema format. Signed-off-by:
Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by:
Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1587720562-15293-1-git-send-email-hayashi.kunihiko@socionext.comSigned-off-by:
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- 11 May, 2020 4 commits
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Jay Fang authored
Reduce unnecessary static memory allocation when CONFIG_ACPI is not enabled. Signed-off-by:
Jay Fang <f.fangjian@huawei.com> Link: https://lore.kernel.org/r/1588991392-24219-1-git-send-email-f.fangjian@huawei.comSigned-off-by:
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Alistair Francis authored
Set use_gpio_descriptors as true to support using generic GPIO lines for the chip select. Signed-off-by:
Alistair Francis <alistair@alistair23.me> Link: https://lore.kernel.org/r/20200511045330.690507-1-alistair@alistair23.meSigned-off-by:
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Kunihiko Hayashi authored
Use devm_platform_get_and_ioremap_resource() to simplify code instead of platform_get_resource() and devm_ioremap_resource(). This also gets the resource that the following code uses. Signed-off-by:
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Kunihiko Hayashi authored
The driver uses devm_ioremap_resource() which is only available when CONFIG_HAS_IOMEM is set, so the driver depends on this option. Signed-off-by:
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- 07 May, 2020 2 commits
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Andy Shevchenko authored
This flag is superfluous in all cases where it's being used, i.e. * ->can_dma() won't be called without dma_inited == 1 * DMA ->exit() callback can rely on txchan and rxchan variables So, get rid of dma_inited flag. Signed-off-by:
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Andy Shevchenko authored
Generic DMA setup doesn't rely on certain type of DMA controller and thus shouldn't use Intel Medfield settings, although it's harmless in this case. Signed-off-by:
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- 06 May, 2020 6 commits
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Jarkko Nikula authored
Elkhart Lake PSE SPI is capable to utilize PSE DMA engine which is described in ACPI. With help of acpi-dma module the support becomes a generic one. Thus, add Elkhart Lake PSE DMA support and generic DMA hooks in SPI DesignWare driver. Signed-off-by:
Jarkko Nikula <jarkko.nikula@linux.intel.com> Signed-off-by:
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Andy Shevchenko authored
In some cases, one of which is coming soon, we would like to have a struct device pointer to request DMA channel. For this purpose propagate it to ->dma_init() callback in DMA ops. Signed-off-by:
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Andy Shevchenko authored
In order to prepare driver for the extension to support newer hardware, add 'mfld' suffix to some related functions. While here, move DMA parameters assignment under existing #ifdef CONFIG_SPI_DW_MID_DMA. There is no functional change intended. Signed-off-by:
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Andy Shevchenko authored
There is no user of few headers without CONFIG_SPI_DW_MID_DMA being set. Move them under condition. While at it, remove unused slab.h there. Signed-off-by:
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Andy Shevchenko authored
spi-dw-mid.c along with spi-dw.h are direct users of irqreturn.h and nothing else is being used from interrupt.h. So, switch them to use the former instead of latter one. While here, move the header under #ifdef CONFIG_SPI_DW_MID_DMA in spi-dw-mid.c. Signed-off-by:
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Andy Shevchenko authored
The actual user of interrupt.h is spi-dw.h and not bus drivers. Move header there. Signed-off-by:
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