- 21 Mar, 2012 40 commits
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Alex Deucher authored
v2: fix check for MC ucode from Tom. Signed-off-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
TN (trinity) uses DP bridges for LVDS and VGA just like llano. Signed-off-by:
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Alex Deucher authored
It's handled via external clock. It should already be protected by the external ss flag, but add an explicit check just in case. Signed-off-by:
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Alex Deucher authored
Signed-off-by:
Alex Deucher <alexdeucher@gmail.com> Signed-off-by:
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Alex Deucher authored
On TN, UNIPHYA always uses PPLL2, UNIPHYB/C/D/E/F can use either PPLL1 or PPLL0. Signed-off-by:
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Alex Deucher authored
DCE6.1 uses EXT_PLL1 for disp eng. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Michel Dänzer authored
v2: agd5f: add new MAX_PIPES param Signed-off-by:
Michel Dänzer <michel.daenzer@amd.com> Reviewed-by:
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Alex Deucher authored
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Alex Deucher authored
Very basic implementation for picking the ring priority. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
This is mostly identical to evergreen/ni, however there are some additional fields in the IV vector for RINGID and VMID. Signed-off-by:
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Alex Deucher authored
RLC handles the interrupt controller and other tasks on the GPU. Signed-off-by:
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Alex Deucher authored
Support both IBs (DE) and CONST IBs (CE). Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
Currently the driver required 5 sets of ucode: 1. pfp - pre-fetch parser, part of the CP 2. me - micro engine, part of the CP 3. ce - constant engine, part of the CP 4. rlc - interrupt controller 5. mc - memory controller Signed-off-by:
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Alex Deucher authored
v2: avoid double free. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
This adds a new chunk id to the CS ioctl to support the INDIRECT_BUFFER_CONST packet. On SI, the CP adds a new engine called the CE (Constant Engine) which runs simulatenously with the DE (Drawing Engine, formerly called the ME). This allows the CP to process two related IBs simultaneously. The CE is tasked with loading the constant data (constant buffers, resource descriptors, samplers, etc.) while the DE loads context register state and issues drawing commands. It's up to the userspace application to sychronize the CE and the DE using special synchronization packets. Signed-off-by:
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Alex Deucher authored
Sets up the VM and adds support for the new VM ioctls. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
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Alex Deucher authored
DCE6 requires a non-0 value for lpAuxRequest for the ProcessAuxChannelTransaction command table. Setting lpAuxRequest to 0 is a special case used by AsicInit for setting up the aux pads. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
Rename the function to better match the functionality. DCPLL became PLL0 on DCE6. Signed-off-by:
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Alex Deucher authored
Each pair of crtcs (0/1, 2/3, 4/5) can be power gated. Make sure the power is applied when the crtc is in use and only power down the pair when both are off. Signed-off-by:
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Alex Deucher authored
The hw no longer has the bits and the table is removed. Signed-off-by:
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Alex Deucher authored
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Alex Deucher authored
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