- 02 Jun, 2014 1 commit
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git://anongit.freedesktop.org/drm-intelDave Airlie authored
- prep refactoring for execlists (Oscar Mateo) - corner-case fixes for runtime pm (Imre) - tons of vblank improvements from Ville - prep work for atomic plane/sprite updates (Ville) - more chv code, now almost complete (tons of different people) - refactoring and improvements for drm_irq.c merged through drm-intel-next - g4x/ilk reset improvements (Ville) - removal of encoder->mode_set - moved audio state tracking into pipe_config - shuffled fb pinning out of the platform crtc modeset callbacks into core code - userptr support (Chris) - OOM handling improvements from Chris, with now have a neat oom notifier which jumps additional debug information. - topdown allocation of ppgtt PDEs (Ben) - fixes and small improvements all over * tag 'drm-intel-next-2014-05-23' of git://anongit.freedesktop.org/drm-intel: (187 commits) drm/i915: Kill private_default_ctx off drm/i915: s/i915_hw_context/intel_context drm/i915: Split the ringbuffers from the rings (3/3) drm/i915: Split the ringbuffers from the rings (2/3) drm/i915: Split the ringbuffers from the rings (1/3) drm/i915: s/intel_ring_buffer/intel_engine_cs drm/i915: disable GT power saving early during system suspend drm/i915: fix possible RPM ref leaking during RPS disabling drm/i915: remove user GTT mappings early during runtime suspend drm/i915: Implement WaVcpClkGateDisableForMediaReset:ctg, elk drm/i915: Fix gen2 and hsw+ scanline counter drm/i915: Draw a picture about video timings drm/i915: Improve gen3/4 frame counter drm/i915: Add a small adjustment to the pixel counter on interlaced modes drm/i915: Hold CRTC lock whilst freezing the planes drm/i915: Only discard backing storage on releasing the last ref drm/i915: Wait for pending page flips before enabling/disabling the primary plane drm/i915: grab the audio power domain when enabling audio on HSW+ drm/i915: don't read HSW_AUD_PIN_ELD_CP_VLD when the power well is off drm/i915: move bsd dispatch index somewhere better ...
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- 30 May, 2014 3 commits
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Dave Airlie authored
This adds an encoder type for DP MST encoders. Reviewed-by:
Todd Previte <tprevite@gmail.com> Signed-off-by:
Dave Airlie <airlied@redhat.com>
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Jani Nikula authored
This makes drm_get_encoder_name() thread safe. Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01\ .ptsecurity.ru Signed-off-by:
Jani Nikula <jani.nikula@intel.com> Reviewed-by:
David Herrmann <dh.herrmann@gmail.com> Signed-off-by:
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Jani Nikula authored
This makes drm_get_connector_name() thread safe. [airlied: fix to build.] Reference: http://lkml.kernel.org/r/645ee6e22cad47d38a2b35c21c8d5fe3@DC1-MBX-01.ptsecurity.ruSigned-off-by:
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- 27 May, 2014 8 commits
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Thierry Reding authored
Commit 9dc40560 (drm/dp: let drivers specify the name of the I2C- over-AUX adapter) introduced a new field but didn't add the proper kernel-doc for it. Signed-off-by:
Thierry Reding <treding@nvidia.com> Reviewed-by:
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David Herrmann authored
shmem_read_mapping_page() uses mapping_gfp_mask(mapping) as default gfp mask. No reason to use shmem_read_mapping_page_gfp() directly if we want the default behavior. Acked-by:
Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by:
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David Herrmann authored
shmem supports page-relocations during swapin since quite some time. It was implemented in: commit bde05d1c Author: Hugh Dickins <hughd@google.com> Date: Tue May 29 15:06:38 2012 -0700 shmem: replace page if mapping excludes its zone The gem-comment about wrongly placed DMA32 pages is no longer valid. Replace it with a proper comment but keep the BUG_ON() to verify correct shmem behavior. Signed-off-by:Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Benoit Taine authored
This issue was reported by coccicheck using the semantic patch at scripts/coccinelle/api/memdup.cocci Signed-off-by:
Benoit Taine <benoit.taine@lip6.fr> Signed-off-by:
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Jean Delvare authored
The shmobile DRM driver is only useful on SuperH and shmobile unless build testing. I am dropping the SuperH dependencies though because the driver doesn't even build there, so in practice it is an arm-only driver for now. Signed-off-by:
Jean Delvare <jdelvare@suse.de> Acked-by:
Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> Signed-off-by:
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Jean Delvare authored
The Renesas R-Car Display Unit driver is only useful on shmobile unless build testing. The LVDS output is useful on an even more reduced hardware set. Signed-off-by:
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Daniel Vetter authored
DRM is pretty much the main user of this stuff (if we ignore the sysfs interface used by X, i.e. by the same gang of people writing the drm drivers). So shovel it into Dave's responsibility to avoid patches getting lost on lkml. With this get_maintainers will rout vgaarb and switcheroo patches correctly. Cc: Alex Williamson <alex.williamson@redhat.com> Cc: Dave Airlie <airlied@redhat.com> Cc: linux-kernel@vger.kernel.org References: https://lkml.org/lkml/2014/5/25/94Signed-off-by:
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Sagar Kamble authored
Started documenting drm properties for drm drivers. This patch provides information about properties in drm, i915, psb and cdv/gma-500. Information about other properties can be added on top of these. v2: Added description of drm properties in armada, exynos, i2c/ch7006, noveau, omap, qxl, radeon, rcar-du v3: Removed "Property Object" column since it is implementation related. Property type column refined.[Ville's review comments] v4: Removed whitespace warnings and minor nits. [Randy's review comments] v5: Restructured output for ENUM properties v6: Review comments on formatting the table. [Laurent's review comments] v7: Minor restructuring. [Laurent's review comments] Cc: Rob Landley <rob@landley.net> Cc: Dave Airlie <airlied@redhat.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Acked-by:
Sagar Kamble <sagar.a.kamble@intel.com> Signed-off-by:
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- 26 May, 2014 4 commits
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Alexandre Courbot authored
The kerneldoc header of ttm_bo_create() was referring to another (nonexisting) function and had a few obsolete or incorrect arguments. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Reviewed-by:
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Daniel Thompson authored
The 800x600 (SVGA) screen resolution was lacking in the set of built-in selectable EDID screen resolutions that can be used to repair misbehaving monitor firmware. This patch adds the related data set and expands the documentation. Note that the SVGA bit occupies a different byte to all the existing users of the established timing bits forcing a rework of the ESTABLISHED_TIMINGS_BITS macro. Tested new EDID on an aged (and misbehaving) industrial LCD panel; existing EDIDs still pass edid-decode's checksum checks. Signed-off-by:
Daniel Thompson <daniel.thompson@linaro.org> Cc: Randy Dunlap <rdunlap@infradead.org> Cc: David Airlie <airlied@linux.ie> Cc: Carsten Emde <C.Emde@osadl.org> Cc: linux-doc@vger.kernel.org Cc: dri-devel@lists.freedesktop.org Reviewed-by:
Alex Deucher <alexander.deucher@amd.com> Signed-off-by:
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Masanari Iida authored
Fix spelling typo in DocBook/drm.tmpl Signed-off-by:
Masanari Iida <standby24x7@gmail.com> Signed-off-by:
Randy Dunlap <rdunlap@infradead.org> Signed-off-by:
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Rob Clark authored
Signed-off-by:
Rob Clark <robdclark@gmail.com> Signed-off-by:
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- 23 May, 2014 1 commit
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Dave Airlie authored
This just adds the defines from the DP 1.2 spec, which we will use later. fix some DP MST to 1.2 MST Signed-off-by:
Jingoo Han <jg1.han@samsung.com>
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- 22 May, 2014 23 commits
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Oscar Mateo authored
It's barely alive now anyway, so give it the "coup de grâce". Signed-off-by:
Oscar Mateo <oscar.mateo@intel.com> Signed-off-by:
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Oscar Mateo authored
Up until now, contexts had one (and only one) backing object that was used by the hardware to save/restore render ring contexts (via the MI_SET_CONTEXT command). Other rings did not have or need this, so our i915_hw_context struct had a 1:1 relationship with a a real HW context. With Logical Ring Contexts and Execlists, this is not possible anymore: all rings need a backing object, and it cannot be reused. To prepare for that, rename our contexts to the more generic term intel_context. No functional changes. Signed-off-by:
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Oscar Mateo authored
Manual cleanup after the previous Coccinelle script. Yes, I could write another Coccinelle script to do this but I don't want labor-replacing robots making an honest programmer's work obsolete (also, I'm lazy). Signed-off-by:
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Oscar Mateo authored
This refactoring has been performed using the following Coccinelle semantic script: @@ struct intel_engine_cs r; @@ ( - (r).obj + r.buffer->obj | - (r).virtual_start + r.buffer->virtual_start | - (r).head + r.buffer->head | - (r).tail + r.buffer->tail | - (r).space + r.buffer->space | - (r).size + r.buffer->size | - (r).effective_size + r.buffer->effective_size | - (r).last_retired_head + r.buffer->last_retired_head ) @@ struct intel_engine_cs *r; @@ ( - (r)->obj + r->buffer->obj | - (r)->virtual_start + r->buffer->virtual_start | - (r)->head + r->buffer->head | - (r)->tail + r->buffer->tail | - (r)->space + r->buffer->space | - (r)->size + r->buffer->size | - (r)->effective_size + r->buffer->effective_size | - (r)->last_retired_head + r->buffer->last_retired_head ) @@ expression E; @@ ( - LP_RING(E)->obj + LP_RING(E)->buffer->obj | - LP_RING(E)->virtual_start + LP_RING(E)->buffer->virtual_start | - LP_RING(E)->head + LP_RING(E)->buffer->head | - LP_RING(E)->tail + LP_RING(E)->buffer->tail | - LP_RING(E)->space + LP_RING(E)->buffer->space | - LP_RING(E)->size + LP_RING(E)->buffer->size | - LP_RING(E)->effective_size + LP_RING(E)->buffer->effective_size | - LP_RING(E)->last_retired_head + LP_RING(E)->buffer->last_retired_head ) Note: On top of this this patch also removes the now unused ringbuffer fields in intel_engine_cs. Signed-off-by: -
Oscar Mateo authored
As advanced by the previous patch, the ringbuffers and the engine command streamers belong in different structs. This is so because, while they used to be tightly coupled together, the new Logical Ring Contexts (LRC for short) have a ringbuffer each. In legacy code, we will use the buffer* pointer inside each ring to get to the pertaining ringbuffer (the actual switch will be done in the next patch). In the new Execlists code, this pointer will be NULL and we will use instead the one inside the context instead. Signed-off-by:
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Oscar Mateo authored
In the upcoming patches we plan to break the correlation between engine command streamers (a.k.a. rings) and ringbuffers, so it makes sense to refactor the code and make the change obvious. No functional changes. Signed-off-by:
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Imre Deak authored
Atm, we disable GT power saving during the end of the suspend sequence in i915_save_state(). Doing the disabling at that point seems arbitrary. One reason to disable it early though is to have a quiescent HW state before we do anything else (for example save registers). So move the disabling earlier, which also takes care canceling of the deferred RPS enabling work done by intel_disable_gt_powersave(). Note that after the move we'll call intel_disable_gt_powersave() only in case modeset is enabled, but that's anyway the only case where we have it enabled in the first place. Signed-off-by:
Imre Deak <imre.deak@intel.com> Reviewed-by:
Robert Beckett <robert.beckett@intel.com> Signed-off-by:
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Imre Deak authored
In commit c6df39b5 Author: Imre Deak <imre.deak@intel.com> Date: Mon Apr 14 20:24:29 2014 +0300 drm/i915: get a runtime PM ref for the deferred GT powersave enabling I added an RPM get-ref when enabling RPS from a deferred work, but forgot to add the corresponding put-ref when canceling the work. This may leave RPM disabled. Note that the race is real since we run the rps enabling with a delayed work item after resume, so leaves enough time (in contrived examples) to fit a quick autoresum in. Signed-off-by:
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Imre Deak authored
Currently user space can access GEM buffers mapped to GTT through existing mappings concurrently while the platform specific suspend handlers are running. Since these handlers may change the HW state in a way that would break such accesses, remove the mappings before calling the handlers. Spotted by Ville. Also Chris pointed out that the lists that i915_gem_release_all_mmaps() walks through need dev->struct_mutex, so take this lock. There is a potential deadlock against a concurrent RPM resume, resolve this by aborting and rescheduling the suspend (Daniel). v2: - take struct_mutex around i915_gem_release_all_mmaps() (Chris, Daniel) Signed-off-by:
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Ville Syrjälä authored
Apparently we need to disable VCP unit clock gating around media reset on g4x. Signed-off-by:
Ville Syrjälä <ville.syrjala@linux.intel.com> Acked-by:
Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by:
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Ville Syrjälä authored
On gen2 the scanline counter behaves a bit differently from the later generations. Instead of adding one to the raw scanline counter value, we must subtract one. On HSW/BDW the scanline counter requires a +2 adjustment on HDMI outputs. DP outputs on the on the other require the typical +1 adjustment. As the fixup we must apply to the hardware scanline counter depends on several factors, compute the desired offset at modeset time and tuck it away for when it's needed. v2: Clarify HSW+ situation Signed-off-by:
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Ville Syrjälä authored
The docs are a bit lacking when it comes to describing when certain timing related events occur in the hardware. Draw a picture which tries to capture the most important ones. v2: Clarify a few details (Imre) v3: Add HSW+ HDMI scanline counter numbers Acked-by:
Akash Goel <akash.goels@gmail.com> Signed-off-by:
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Ville Syrjälä authored
Currently the logic to fix up the frame counter on gen3/4 assumes that start of vblank occurs at vblank_start*htotal pixels, when in fact it occurs htotal-hsync_start pixels earlier. Apply the appropriate adjustment to make the frame counter more accurate. Also fix the vblank start position for interlaced display modes. Reviewed-by:
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Ville Syrjälä authored
In interlaced modes, the pixel counter counts all pixels, so one field will have htotal more pixels. In order to avoid the reported position from jumping backwards when the pixel counter is beyond the length of the shorter field, just clamp the position the length of the shorter field. This matches how the scanline counter based position works since the scanline counter doesn't count the two half lines. Signed-off-by:
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Chris Wilson authored
Daniel keeps on ramping up the warning level of the DRM and our display core to make it complain whenever the locking rules are not followed. This caught commit 24576d23 Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Tue Mar 26 09:25:45 2013 -0700 drm/i915: enable VT switchless resume v3 introducing an unlocked access to the CRTC whilst disabling it for suspend. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=78114Signed-off-by:
Chris Wilson <chris@chris-wilson.co.uk> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by:
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Chris Wilson authored
Before purging our pages (as opposed to copying back the contents from the GPU), make sure that there is not an exposed CPU mmapping through which the user can inspect the results. Regression from commit 5537252b Author: Chris Wilson <chris@chris-wilson.co.uk> Date: Tue Mar 25 13:23:06 2014 +0000 drm/i915: Invalidate our pages under memory pressure Testcase: igt/gem_mmap/new-object Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=79005Signed-off-by:
Guo Jinxian <jinxianx.guo@intel.com> Signed-off-by:
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Ville Syrjälä authored
We have to write to the primary plane base address registrer when we enable/disable the primary plane in response to sprite coverage. Those writes will cause the flip counter to increment which could interfere with the detection of CS flip completion. We could end up completing CS flips before the CS has even executed the commands from the ring. To avoid such issues, wait for CS flips to finish before we toggle the primary plane on/off. v2: Rebased due to atomic sprite update changes Testcase: igt/kms_mmio_vs_cs_flip/setplane_vs_cs_flip Signed-off-by:
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Paulo Zanoni authored
With the current code, we unconditionally touch HSW_AUD_PIN_ELD_CP_VLD, which means we can touch it when the power well is off, and that will trigger an "Unclaimed register" message. Just adding the intel_crtc->config.has_audio should already avoid the unclaimed register messsages, but since we actually need the power well to make the Audio code work, it makes sense to also grab the audio power domain reference, and release it when it's not needed anymore. I used IGT's pm_rpm to reproduce this bug, but it can probably be reproduced on other tests that do modesets. I'm using a machine with eDP+HDMI connected. Regression introduced by: commit acfa75b0 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Apr 24 23:54:51 2014 +0200 drm/i915: Simplify audio handling on DDI ports Credits to Daniel for suggesting this implementation. Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
Paulo Zanoni <paulo.r.zanoni@intel.com> Signed-off-by:
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Paulo Zanoni authored
Because this will trigger "Unclaimed register" messages. All I need to reproduce this problem is to boot my HSW machine with eDP+HDMI connected. Regression introduced by: commit 9ed109a7 Author: Daniel Vetter <daniel.vetter@ffwll.ch> Date: Thu Apr 24 23:54:52 2014 +0200 drm/i915: Track has_audio in the pipe config Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Signed-off-by:
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Daniel Vetter authored
Adding stuff at the bottom is really no how this should be done, since that's the place for ums/dri dungeons. This was added in commit a8ebba75 Author: Zhao Yakui <yakui.zhao@intel.com> Date: Thu Apr 17 10:37:40 2014 +0800 drm/i915: Use the coarse ping-pong mechanism based on drm fd to dispatch the BSD command on BDW GT3 Also add a note to prevent this from happening again - people really should be less lazy and take more time to look for a good home of their new driver-global state. Cc: Imre Deak <imre.deak@intel.com> Cc: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by:
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Ville Syrjälä authored
Gen2 reports FIFO underruns whenever no planes are enabled on the pipe. So in order to avoid false positives we must enable the FIFO underrun reporting only when at least one plane is enabled on the pipe. For now just move the underrun reporting enable/disable points to the other side of the plane enable/disable point. That doesn't cover cases when we turn off all the planes for the pipe but leave the pipe running on purpose, but it's better than the current situation. On gen4+ we can actually move the underrun reporting enable/disable to the opposite ends of the crtc enable/disable hooks. I suppose in theory we could leave the underrun reporting enabled all the time, except on VLV where PIPESTAT stops working when the display power well is down. If we ever get around to unifying the PIPESTAT irq handling for all gmch platforms, we should still follow the VLV route for other platforms. It would also micro-optimize the irq handler a bit since we could then skip the PIPESTAT reads for all disabled pipes. Gen3 is still a mystery, but for now I'm going to assume it behaves like gen4+. Signed-off-by:
Thomas Wood <thomas.wood@intel.com> Signed-off-by:
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Ville Syrjälä authored
Checking whether the error interrupt was enabled or not isn't really necessary when we check for uncleared FIFO underruns. If it was enabled we'll race with the interrupt handler a bit, but that seems OK as we still claim the interrupt. Signed-off-by:
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Ville Syrjälä authored
FIFO underruns don't generate interrupts on gmch platforms, so if we want to know whether a modeset triggered FIFO underruns we need to explicitly check for them. As a modeset on one pipe could cause underruns on other pipes, check for underruns on all pipes. Signed-off-by:
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