- 06 Jun, 2019 2 commits
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xinhui pan authored
gpu reset will run late_init and schedule the late_init_work. if we keep triggering gpu reset in a short time, there are potenial races. Signed-off-by:
xinhui pan <xinhui.pan@amd.com> Reviewed-by:
Feifei Xu <Feifei.Xu@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Mauro Carvalho Chehab authored
This file was renamed, but docs weren't updated accordingly. WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -function PRIME Buffer Sharing ./drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c' failed with return code 1 WARNING: kernel-doc './scripts/kernel-doc -rst -enable-lineno -internal ./drivers/gpu/drm/amd/amdgpu/amdgpu_prime.c' failed with return code 2 Fixes: 2fbd6f94 ("drm/amdgpu: rename amdgpu_prime.[ch] into amdgpu_dma_buf.[ch]") Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Mauro Carvalho Chehab <mchehab+samsung@kernel.org> Signed-off-by:
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- 31 May, 2019 38 commits
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Chunming Zhou authored
add ticket for display bo, so that it can preempt busy bo. v2: fix stupid rebase error Signed-off-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Signed-off-by:
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Christian König authored
BOs on the LRU might be blocked during command submission and cause OOM situations. Avoid this by blocking for the first busy BO not locked by the same ticket as the BO we are searching space for. v10: completely start over with the patch since we didn't handled a whole bunch of corner cases. Signed-off-by: -
Christian König authored
Move BOs which are currently in a lower domain to the new LRU before allocating backing space while validating. This makes sure that we always have enough entries on the LRU to allow for other processes to wait for an operation to complete. v2: generalize the test v3: fix rebase error Signed-off-by:
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Christian König authored
We tried this once before, but that turned out to be more complicated than thought. With all the right prerequisites it looks like we can do this now. Signed-off-by:
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Christian König authored
If drivers don't prefer a system memory placement they should not but it into the placement list first. Signed-off-by:
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Christian König authored
When a signal arrives we should return immediately for handling it and not try other placements first. Signed-off-by:
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Christian König authored
We are already doing this for DMA-buf imports and also for amdgpu VM BOs for quite a while now. If this doesn't run into any problems we are probably going to stop removing BOs from the LRU altogether. v2: drop BUG_ON from ttm_bo_add_to_lru Signed-off-by:
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Emily Deng authored
Issue: Will have follow error when reload driver: [ 3986.567739] sysfs: cannot create duplicate filename '/devices/pci0000:00/0000:00:07.0/drm_dp_aux_dev' [ 3986.567743] CPU: 6 PID: 1767 Comm: modprobe Tainted: G OE 5.0.0-rc1-custom #1 [ 3986.567745] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS Ubuntu-1.8.2-1ubuntu1 04/01/2014 [ 3986.567746] Call Trace: ...... [ 3986.567808] drm_dp_aux_register_devnode+0xdc/0x140 [drm_kms_helper] ...... [ 3986.569081] kobject_add_internal failed for drm_dp_aux_dev with -EEXIST, don't try to register things with the same name in the same directory. Reproduce sequences: 1.modprobe amdgpu 2.modprobe -r amdgpu 3.modprobe amdgpu Root cause: When unload driver, it doesn't unregister aux. v2: Don't use has_aux Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by:
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Emily Deng authored
For the VF, some registers only could be programmed with RLC. Signed-off-by:
Trigger Huang <Trigger.Huang@amd.com> Signed-off-by:
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Oak Zeng authored
Signed-off-by:
Oak Zeng <Oak.Zeng@amd.com> Reviewed-by:
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Aric Cyr authored
[Why] We only want to manual trigger end-of-frame when the bottom-most pipe is flipped to prevent overlays from ending the frame too early. [How] Check that the manual trigger is only firing on bottom plane. Signed-off-by:
Aric Cyr <aric.cyr@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
Leo Li <sunpeng.li@amd.com> Signed-off-by:
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Krunoslav Kovac authored
[Why] There's some unnecessary mem allocation for CS_TFM_ID. What's worse, it depends on LUT size and since it's 4K for CS_TFM_1D, it is 16x bigger than in regular case when it's actually needed. This leads to some crashes in stress conditions. [How] Skip ramp combining designed for RGB256 and DXGI gamma with CS_TFM_1D. Signed-off-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] For commits with allow_modeset=false and CRTC degamma changes the planes aren't reset. This results in incorrect rendering. [How] Reset the planes when color management has changed on the CRTC. Technically this will include regamma changes as well, but it doesn't really after legacy userspace since those commit with allow_modeset=true. Signed-off-by:
Harry Wentland <Harry.Wentland@amd.com> Acked-by:
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Eryk Brol authored
[Why] Some backlight tests fail due to backlight settling taking too long. This happens because the step size used to change backlight levels is too small. [How] 1. Change the size of the backlight gain step size 2. Change how DMCU firmware gets the step size value so that it is passed in by driver during DMCU initn Signed-off-by:
Eryk Brol <eryk.brol@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] Some displays take some time to power up AUX CH once they are put into D3 state via write to DPCD 600h=2. Interestingly enough, some display may simply NACK, but some might also ACK with a bunch of 0s, which can cause issues with receiver cap retrieval. Note that not all DPCD address return 0s, but in particular it has been observed on some higher DPCD address such as DPCD 2200h, etc. [How] Based on spec, receiver will monitor differential signal while in D3 and AUX CH is in low power mode. When detected, it may allow up to 1 ms to power up AUX CH and reply. If we read Sink power state D3, we should add 1 ms delay to satisfy this spec requirement. Signed-off-by:
Anthony Koo <anthony.koo@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Eric Bernstein authored
* Pull duplicate audio_clock_info struct to stream_encoder.h * Generalize sec_gsp7* to sec_gsp_pps* * Expose enc1 and enc2 stream encoder audio funcs Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Reviewed-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by:
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Daniel He authored
[Description] This is cause by failing to read link caps from driver. Signed-off-by:
Daniel He <daniel.he@amd.com> Reviewed-by:
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Ilya Bakoulin authored
Adding writeback_config enum to vba_vars_st, replacing old flag. Initialize to dm_normal. Signed-off-by:
Ilya Bakoulin <Ilya.Bakoulin@amd.com> Reviewed-by:
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Eric Yang authored
[Why] Some HW specific implementations can be pulled out into clk_mgr.c. [How] * Pull get_active_display_cnt out to clk_mgr. * Pull out shared logic in set_dispclk and set_dprefclk Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Eric Yang authored
[why] Value read from SMU is 16 bits, not 32. [How] Fix type, and add wm_type enum in preparation for future interfaces. Signed-off-by:
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Anthony Koo authored
[Why] Modern Standby may toggle display adapter state between D0 and D3 state unpredictably. But events that cause transition to D0 are not always resulting in a display light up scenario. Modern eDP panels should be able to power on panel logic quickly upon VDD going high. Based on spec, the T3 time between VDD on and HPD high can be between 0 and 80 ms. Doing any tricky sorts of optimization by powering on panel VDD early during D0 transition on can negatively impact other features due to unnecessary power drain and toggling when final system state does not intend for the panel to be lit up. We need OEMs to source higher end panels that have T3 time close to 0 if they want quick S3/Modern Standby resume times. [How] Remove panel VDD power on in init_hw Signed-off-by:
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Su Sung Chung authored
[why] during It's possible to call dcn_validate_bandwidth with no plane. In that case, as we are only intersted in if output timing is supported or not, even if we cannot support native resolution, we still want to support lower resolution if it is valid [how] if there exist no surface, make viewport/rec_out size at max 1080p. It is already known that 1080p x 6(max # of pipes) is supported, so if we fail validation, it is because of the stream Signed-off-by:
Su Sung Chung <Su.Chung@amd.com> Reviewed-by:
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Su Sung Chung authored
[why] by adding fast_validate flag, we are skipping some portion of dcn_validate_bandwidth code that is not necessary for mode validation. However we have a bug where it does not calculate v->total_data_read_bandwidth, which is one of the factors determines the result of the validation, and therefore report false positive during mode validation. [how] add calculation of v->total_data_read_bandwidth outside of the region that is guarded by fast_validate flag Signed-off-by:
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Aric Cyr authored
Signed-off-by:
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Chris Park authored
[Why] link-specific functions should reside in dc_link.c [How] Move them there. Signed-off-by:
Chris Park <Chris.Park@amd.com> Reviewed-by:
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Jun Lei authored
Add min_dcfclk_mhz to bounding box overrides. Signed-off-by:
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Eric Yang authored
[Why] Better organization [How] Move clk_mgr files under dc/clk_mgr Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Acked-by:
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Paul Hsieh authored
[Why] 1. DMCU is not running on some platform but driver still send ABM command. It may cause assert due to DMCU is not alive. 2. To make sure PSR disable when driver disable [How] 1. Add dmcu_is_running in ABM struct, driver can check this flag to determine driver should send ABM command or not. 2. Send PSR disable command when destroy PSR Signed-off-by:
Paul Hsieh <paul.hsieh@amd.com> Reviewed-by:
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Eryk Brol authored
[Why] In the previous implementation DRR event sometimes came in during FP2 region which is a keep-out zone. This would cause the frame not to latch until the next frame which resulted in heavy flicker. To fix this we need to make sure that it triggers in the BP. [How] 1. Remove DRR programming during flip 2. Setup manual trigger for DRR event and trigger it after surface programming is complete Signed-off-by:
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Krunoslav Kovac authored
GSL is a form of locking that can be used to synchronize pipes in a pipe-split configurations when async flip is used. Add the registers here. Signed-off-by:
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Eryk Brol authored
[Why] Previously there were 2 consecutive calls being made to disable audio stream. The first one disabled the audio stream, and the second one went through and also tried to disable the audio stream causing BACO entry issues due to the ASIC appearing busy. [How] 1. Add a status field to the audio struct which stores enabled/disabled info 2. In the calls to enable/disable audio stream check if we're already in the desired state before executing the function Signed-off-by:
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Wenjing Liu authored
[why] stream id should uniquely identify an instance of stream. the copy constructor should be treated as a new stream instance. [how] assign a new stream id in this copy constructor. Signed-off-by:
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Eric Yang authored
This macro is specificly used by RV1. Move it to the appropriate location. Signed-off-by:
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Gary Kattan authored
Add vtable entries for de-alpha and bias color management interfaces. Move piece-wise transfer function registers to a helper list for future reuse. Signed-off-by:
Gary Kattan <gary.kattan@amd.com> Reviewed-by:
Nevenko Stupar <Nevenko.Stupar@amd.com> Acked-by:
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Hugo Hu authored
We can’t use hardcoded SRGB ROM for output TF if we have GAMMA_CS_TFM_1D (unless we know 1D LUT is identity), so we never want to return here early. We apply the LUT part of ColorTransform3x4 only in apply_lut_1d() which is called near the end of that function. Signed-off-by:
Hugo Hu <hugo.hu@amd.com> Reviewed-by:
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Eric Yang authored
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by:
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Emily Deng authored
As it will destroy clear_state_obj, and also will unpin it in the gfx_v9_0_sw_fini, so don't need to call amdgpu_bo_free_kernel in gfx_v9_0_sw_fini, or it will have unpin warning. Signed-off-by:
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xinhui pan authored
injection need a valid gpu address. Signed-off-by:
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