- 15 May, 2018 40 commits
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo (Sunpeng) Li authored
Hardware understands the regamma LUT as a piecewise linear function, with points spaced exponentially along the range. We previously programmed the LUT for range [2^-10, 2^0). This causes (normalized) color values of 1 (=2^0) to miss the programmed LUT, and fall onto the end region. For DCE, the end region is extrapolated using a single (base, slope) pair, using the max y-value from the last point in the curve as base. This presents a problem, since this value affects all three color channels. Scaling down the intensity of say - the blue regamma curve - will not affect it's end region. This is especially noticiable when using RedShift. It scales down the blue and green channels, but leaves full-intensity colors unshifted. Therefore, extend the range to cover [2^-10, 2^1) by programming another hardware segment, containing only one point. That way, we won't be hitting the end region. Note that things are a bit different for DCN, since the end region can be set per-channel. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
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Eric Bernstein authored
Signed-off-by:
Eric Bernstein <eric.bernstein@amd.com> Reviewed-by:
Nikola Cornij <Nikola.Cornij@amd.com> Acked-by:
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Roman Li authored
Adding missing call to cache current backlight values. Otherwise the brightness resets to default value on resume. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Eric Yang authored
Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Harry Wentland authored
Even though this is required for degamma since DCE HW only supports a couple predefined LUTs we can just program the LUT directly for regamma. This fixes dark screens which occurs when we program regamma to bypass while degamma is using srgb LUT. Signed-off-by:
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Shirish S authored
amdgpu_ib_ring_tests() runs test IB's on rings at boot contributes to ~500 ms of amdgpu driver's boot time. This patch defers it and ensures that its executed in amdgpu_info_ioctl() if it wasn't scheduled. V2: Use queue_delayed_work() & flush_delayed_work(). V3: removed usage of separate wq, ensure ib tests is run before enabling clockgating. Signed-off-by:Shirish S <shirish.s@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
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Mikita Lipski authored
Filling the smu10_store_cc6_data based on the implementation of Windows Powerplay. There is an uncertainty with one of the parameters passed to the function pstate_switch_disable - is not a part of smu10 private data structure. So in the function its just ignored. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Rex Zhu <Rex.Zhu@amd.com> Acked-by:
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Mikita Lipski authored
The function is never implemented for raven on linux. It follows similair implementation as on windows. SMU still needs to notify SMC and copy WM table, which is added here. But on other Asics such as Vega this step is not implemented. Signed-off-by:
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Christian König authored
If a per VM BO ends up in a allowed domain it never moves back into the prefered domain. v2: move the extra handling into amdgpu_vm_bo_update when we exit the state machine. Make memory type handling generic. Signed-off-by:Chunming Zhou <david1.zhou@amd.com> Signed-off-by:
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Christian König authored
This reverts commit 7d1ca1325260a9e9329b10a21e3692e6f188936f. Makes fallback handling to complicated. This is just a feature for the GEM interface and shouldn't leak into the core BO create function. The intended change to preserve the preferred domains is implemented in a follow up patch. Signed-off-by:
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Christian König authored
This reverts commit 6f51d28bfe8e1a676de5cd877639245bed3cc818. Makes fallback handling to complicated. This is just a feature for the GEM interface and shouldn't leak into the core BO create function. Signed-off-by:
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Rex Zhu authored
Reviewed-by:
Huang Rui <ray.huang@amd.com> Signed-off-by:
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Rex Zhu authored
smu firmware do not update response register immediately under some delay tasks, we may read out the original value. so need to clear the register before send smu message. Acked-by:
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Rex Zhu authored
Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, User need to set start time and end time, firmware can calculate the average vddc/vddci/max power. but the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. so this struct can't be suitable for all asics. Acked-by:
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Rex Zhu authored
pkgpwr is the average gpu power of 100ms. it is calculated by firmware in real time. 1. we can send smu message PPSMC_MSG_GetCurrPkgPwr to read currentpkgpwr directly. 2. On Fiji/tonga/bonaire/hawwii, without PPSMC_MSG_GetCurrPkgPwr support. Send PPSMC_MSG_PmStatusLogStart/Sample to let smu write currentpkgpwr to ixSMU_PM_STATUS_94. driver can read pkgpwr from ixSMU_PM_STATUS_94. Acked-by:
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Rex Zhu authored
we don't have limit of [50ms, 4sec] sampling period. smu calculate average gpu power in real time. we can read average gpu power through smu message or read special register. This reverts commit 462d8dcc9fec0d89f1ff6a1f93f1d4f670878c71. Acked-by:
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Emily Deng authored
issue: there are VMC page fault occurred if force APP kill during 3dmark test, the cause is in entity_fini we manually signal all those jobs in entity's queue which confuse the sync/dep mechanism: 1)page fault occurred in sdma's clear job which operate on shadow buffer, and shadow buffer's Gart table is cleaned by ttm_bo_release since the fence in its reservation was fake signaled by entity_fini() under the case of SIGKILL received. 2)page fault occurred in gfx' job because during the lifetime of gfx job we manually fake signal all jobs from its entity in entity_fini(), thus the unmapping/clear PTE job depend on those result fence is satisfied and sdma start clearing the PTE and lead to GFX page fault. fix: 1)should at least wait all jobs already scheduled complete in entity_fini() if SIGKILL is the case. 2)if a fence signaled and try to clear some entity's dependency, should set this entity guilty to prevent its job really run since the dependency is fake signaled. v2: splitting drm_sched_entity_fini() into two functions: 1)The first one is does the waiting, removes the entity from the runqueue and returns an error when the process was killed. 2)The second one then goes over the entity, install it as completion signal for the remaining jobs and signals all jobs with an error code. v3: 1)Replace the fini1 and fini2 with better name 2)Call the first part before the VM teardown in amdgpu_driver_postclose_kms() and the second part after the VM teardown 3)Keep the original function drm_sched_entity_fini to refine the code. v4: 1)Rename entity->finished to entity->last_scheduled; 2)Rename drm_sched_entity_fini_job_cb() to drm_sched_entity_kill_jobs_cb(); 3)Pass NULL to drm_sched_entity_fini_job_cb() if -ENOENT; 4)Replace the type of entity->fini_status with "int"; 5)Remove the check about entity->finished. Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Signed-off-by:
Emily Deng <Emily.Deng@amd.com> Reviewed-by:
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Andrey Grodzovsky authored
Reserved VRAM is used to avoid overriding pre OS FB. Once our display stack takes over we don't need the reserved VRAM anymore. v2: Remove comment, we know actually why we need to reserve the stolen VRAM. Fix return type for amdgpu_ttm_late_init. v3: Return 0 in amdgpu_bo_late_init, rebase on changes to previous patch v4: rebase v5: For GMC9 reserve always just 9M and keep the stolem memory around until GART table curruption on S3 resume is resolved. Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Alex Deucher authored
Steal 9 MB for vga emulation and fb if vga is enabled, otherwise, steal enough to cover the current display size as set by the vbios. If no memory is used (e.g., secondary or headless card), skip stolen memory reserve. v2: skip reservation if vram is limited, address Christian's comments v3: squash in fix from Harry Reviewed-and-Tested-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com> (v2) Signed-off-by:Alex Deucher <alexdeucher@gmail.com>
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Alex Deucher authored
Use amdgpu_ring_emit_reg_write_reg_wait. On engines that support it, it provides a write and wait in a single packet which avoids a missed ack if a world switch happens between the request and waiting for the ack. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back using the helper since the engines doesn't have a oneshot packet. Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back in a single oneshot packet. This is needed to send a tlb invalidation and wait for ack in a single operation. v2: squash sdma hang fix into this patch Reviewed-by:
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Alex Deucher authored
This adds support for writing and reading back in a single oneshot packet. This is needed to send a tlb invalidation and wait for ack in a single operation. v2: squash the gfx ring stall fix Reviewed-by:
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Alex Deucher authored
This callback writes a value to a register and then reads back another register and waits for a value in a single operation. Provide a helper function using two operations for engines that don't support this opertion. Reviewed-by:
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Alex Deucher authored
It doesn't actually upload any firmware is just checks the version. The actual upload happens in the gmc modules. Reviewed-by:
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Alex Deucher authored
Fiji uses a different register than other smu7 asics, but we already have this info in the base driver so just use that. Reviewed-by:
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Harry Wentland authored
This seems to cause flickering and lock-ups for a wide range of users. Revert until we've found a proper fix for the flickering and lock-ups. This reverts commit 36cc549d. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
Michel Dänzer <michel.daenzer@amd.com> Signed-off-by:
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Harry Wentland authored
This reverts commit cd2d6c92. Cc: Shirish S <shirish.s@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by:
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Alex Deucher authored
Userspace needs to query this value to work around a hw bug in certain cases. Acked-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Signed-off-by:
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Christian König authored
Make sure the transfered BO is never destroy before the transfer BO. Signed-off-by:
Roger He <Hongbo.He@amd.com> Signed-off-by:
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Rex Zhu authored
Only check smc running state before start smu. Reviewed-by:
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Rex Zhu authored
Reviewed-by:
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Kenneth Feng authored
To expose the right dpm levels to the sysfs Signed-off-by:
Kenneth Feng <kenneth.feng@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Kenneth Feng authored
To apply on Vega12 for more than 8 gfx dpm levels Signed-off-by:
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Kenneth Feng authored
pp_dpm_sclk/pp_dpm_mclk in sysfs implemented to force gfxclk/uclk dpm level for Vega12 Signed-off-by:
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Rex Zhu authored
1. fix set vce clocks failed on Cz/St which lead 1s delay when boot up. 2. remove the workaround in vce_v3_0.c Reviewed-by:
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Rex Zhu authored
fix the issue set uvd clock failed on CZ/ST which lead 1s delay when boot up. Reviewed-by:
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