- 07 Mar, 2017 40 commits
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Alexandre Courbot authored
I had the brilliant idea to "improve" the binary format by removing a useless indirection in the HS binary files. In the end it just makes things more complicated than they ought to be as NVIDIA-provided files need to be adapted. Since the format used can be identified by the header, support both. Signed-off-by:
Alexandre Courbot <acourbot@nvidia.com> Signed-off-by:
Ben Skeggs <bskeggs@redhat.com>
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Alexandre Courbot authored
If the load and unload falcons are different, then a different bootloader must also be used. Support this case. Signed-off-by:
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Alexandre Courbot authored
Since the HS blobs are provided and signed by NVIDIA, we cannot expect always-consistent behavior. In this case, on GP10x the unload blob may return 0x1d even though things have run perfectly well. This behavior has been confirmed by NVIDIA. So let the callers of the run_blob() hook receive the blob return's value (a positive integer) and decide what it means. This allows us to workaround the 0x1d code instead of issuing an error. Signed-off-by:
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Alexandre Courbot authored
On some secure boot instances (e.g. gp10x) the load and unload blobs do not run on the same falcon. Support this case by introducing a new member to the ACR structure and making related functions take the falcon to use as an argument instead of assuming the boot falcon is to be used. The rule is that the load blob can be run on either the SEC or PMU falcons, but the unload blob must be always run on PMU. Signed-off-by:
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Alexandre Courbot authored
Share elements of r361 that will be reused in other ACRs. Signed-off-by:
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Alexandre Courbot authored
Support running a message queue firmware on SEC. Signed-off-by:
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Alexandre Courbot authored
Add support for running the ACR binary on the SEC falcon. Signed-off-by:
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Alexandre Courbot authored
The start address used for secure blobs is not unique to the ACR, but rather blob-dependent. Remove the unique member stored in the ACR structure and make the load function return the start address for the current blob instead. Signed-off-by:
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Alexandre Courbot authored
ACR firmware from r364 on need a shadow region for the ACR to copy the WPR region into. Add a flag to indicate that a shadow region is required and manage memory allocations accordingly. Signed-off-by:
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Alexandre Courbot authored
Add support for running a msgqueue on the SEC2 falcon. Signed-off-by:
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Alexandre Courbot authored
On SEC, DMEM is unaccessible by the CPU when the falcon is running in LS mode. This makes communication with the firmware using DMEM impossible. For this purpose, a new kind of memory (EMEM) has been added. It works similarly to DMEM, with the difference that its address space starts at 0x1000000. For this reason, it makes sense to treat it like a special case of DMEM. Signed-off-by:
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Alexandre Courbot authored
All falcons have their FBIF registers starting at offset 0x600, with the exception of the PMU and NVENC engines. Signed-off-by:
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Alexandre Courbot authored
Not all falcons have a debug register, and it is not always found at the same offset. Signed-off-by:
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Alexandre Courbot authored
SEC2 is the name given by NVIDIA to the SEC engine post-Fermi (reasons unknown). Even though it shares the same address range as SEC, its usage is quite different and this justifies a new engine. Add this engine and make TOP use it all post-TOP devices should use this implementation and not the older SEC. Also quickly add the short gp102 implementation which will be used for falcon booting purposes. Signed-off-by:
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Alexandre Courbot authored
gp10x' secure boot requires a blob to be run on NVDEC. Expose the falcon through a dummy device. Signed-off-by:
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Alexandre Courbot authored
Reading registers at device construction time can be harmful, as there is no guarantee the underlying engine will be up, or in its runtime configuration. Defer register reading to the oneinit() hook and update users accordingly. Signed-off-by:
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Alexandre Courbot authored
Both registers allow to bind a new context, but NXTCTX will work on all falcons, while legacy NEW_INSTBLK is reserved to PMU. After setting NXTCTX we trigger a context switch by writing 0x090 and 0x0a4. Signed-off-by:
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Alexandre Courbot authored
Enable the PMU firmware in gm20b, managed by secure boot. Signed-off-by:
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Alexandre Courbot authored
gm20b PMU firmware is driven by a msgqueue, so connect relevant PMU hooks to their msgqueue counterparts. Signed-off-by:
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Alexandre Courbot authored
The ACR firmware may return no error but fail nonetheless. Such cases can be detected by verifying that the WPR region has been properly set in FB. If this is not the case, this is an error, but the unload firmware should still not be run. Signed-off-by:
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Alexandre Courbot authored
PMU support has been enabled for r352 ACR, but it must remain optional if we want to preserve existing user-space that do not include it. Allow ACR to be instanciated with a list of optional LS falcons, that will not produce a fatal error if their firmware is not loaded. Also change the secure boot bootstrap logic to be able to fall back to legacy behavior if it turns out the boot falcon's LS firmware cannot be loaded. Signed-off-by:
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Alexandre Courbot authored
Add the PMU bootloader generator and PMU LS ops that will enable proper PMU operation if the PMU falcon is designated as managed. Signed-off-by:
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Alexandre Courbot authored
Adapt secboot's behavior if a PMU firmware is present, in particular the way LS falcons are reset. Without PMU firmware, secboot needs to be performed again from scratch so all LS falcons are reset. With PMU firmware, we can ask the PMU's ACR unit to reset a specific falcon through a PMU message. As we must preserve the old behavior to avoid breaking user-space, add a few conditionals to the way falcons are reset. Signed-off-by:
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Alexandre Courbot authored
Allow secboot to load a LS PMU firmware. LS PMU is one instance of firmwares based on the message queue mechanism, which is also used for other firmwares like SEC, so name its source file accordingly. Signed-off-by:
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Alexandre Courbot authored
NVIDIA-provided PMU firmware is controlled by a msgqueue. Add a member to the PMU structure as well as the required cleanup code if this feature is used. Signed-off-by:
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Alexandre Courbot authored
Add support for the msgqueue firmware used to process PMU commands for gm20b. Signed-off-by:
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Alexandre Courbot authored
A message queue firmware implements a specific protocol allowing the host to send "commands" to a falcon, and the falcon to reply using "messages". This patch implements the common part of this protocol and defines the interface that the host can use. Due to the way the firmware is developped internally at NVIDIA (where kernel driver and firmware evolve in lockstep), firmwares taken at different points in time can have frustratingly subtle differences that must be taken into account. This code is architectured to make implementing such differences as easy as possible. Signed-off-by:
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Alexandre Courbot authored
Add the ability for LS firmwares to declare a post-run hook that is invoked right after the HS firmware is executed. This allows them to e.g. write some initialization data into the falcon's DMEM. Signed-off-by:
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Alexandre Courbot authored
As different firmare versions use different HS descriptor formats, we need to abstract this part as well. Signed-off-by:
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Alexandre Courbot authored
This structure does not need to be shared anymore. Signed-off-by:
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Alexandre Courbot authored
This allows the bootloader descriptor generation code to not rely on specialized ls_ucode_img structures, making it reusable in other instances. Signed-off-by:
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Alexandre Courbot authored
Offsets were not properly computed. This went unnoticed because we are only using one app for now. Signed-off-by:
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Alexandre Courbot authored
Using 32-bit integers would trim the WPR address if it is allocated above 4GB. Signed-off-by:
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Alexandre Courbot authored
A WPR region smaller than 256K will result in secure boot failure. Adjust the minimal size. Signed-off-by:
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Alexandre Courbot authored
The WPR address parameter of the ls_write_wpr hook was defined as a u32, which will very likely overflow on boards with more than 4GB VRAM. Signed-off-by:
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Alexandre Courbot authored
Check at contruction time that we have support for all the LS firmwares asked by the caller. Signed-off-by:
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Alexandre Courbot authored
Remove a leftover that became obsolete with the falcon interface. Signed-off-by:
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Alexandre Courbot authored
All IMEM registers are duplicated per port. Signed-off-by:
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Alexandre Courbot authored
DMEM registers are replicated with a stride of 8 bytes. Signed-off-by:
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Alexandre Courbot authored
The falcon library may be used concurrently, especially after the introduction of the msgqueue interface. Make it safe to use it that way. Signed-off-by:
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