- 15 Nov, 2016 6 commits
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Chen-Yu Tsai authored
The sunxi pinctrl driver only caches whatever pinconf setting was last set on a given pingroup. This is not particularly helpful, nor is it correct. Fix this by actually reading the hardware registers and returning the correct results or error codes. Also filter out unsupported pinconf settings. Since this driver has a peculiar setup of 1 pin per group, we can support both pin and pingroup pinconf setting read back with the same code. The sunxi_pconf_reg helper and code structure is inspired by pinctrl-msm. With this done we can also claim to support generic pinconf, by setting .is_generic = true in pinconf_ops. Also remove the cached config value. The behavior of this was never correct, as it only cached 1 setting instead of all of them. Since we can now read back settings directly from the hardware, it is no longer required. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Acked-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Chen-Yu Tsai authored
According to pinconf-generic.h, the argument for PIN_CONFIG_BIAS_PULL_{DOWN,UP} is non-zero if the bias is enabled with a pull up/down resistor, zero if it is directly connected to VDD or ground. Since Allwinner hardware uses a weak pull resistor internally, the argument should be 1. Signed-off-by: -
Chen-Yu Tsai authored
In the recently refactored sunxi pinctrl library, we are only allocating one set of pin configs for each pinmux setting node. When the pinctrl_map structure is freed, the pin configs should also be freed. However the code assumed the first map would contain the configs, which actually never happens, as the mux function map gets added first. The proper way to do this is to look through all the maps and free the first one whose type is actually PIN_MAP_TYPE_CONFIGS_GROUP. Also slightly expand the comment explaining this. Fixes: f233dbca ("pinctrl: sunxi: Rework the pin config building code") Signed-off-by:
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Paul Gortmaker authored
None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get the exact same change, so they are handled in batch. Changes are (1) use builtin_platform_driver, (2) use init.h header (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE, (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags and (6) drop ".remove" code and prevent sysfs unbind attempts to call ".remove". Once this is done, the shared remove function in wmt.[ch] is no longer used and hence it is removed as well. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We also delete the MODULE_LICENSE etc. tags since all that information is already contained at the top of each file in the comments. Cc: Tony Prisk <linux@prisktech.co.nz> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: linux-gpio@vger.kernel.org Signed-off-by:
Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by:
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Chanwoo Choi authored
This patch add the support of GPF[1-5] pin of Exynos5433 SoC. The GPFx need to support the multiple memory map because the registers of GPFx are located in the different domain. Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Signed-off-by:
Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by:
Chanwoo Choi <cw00.choi@samsung.com> Signed-off-by:
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Chanwoo Choi authored
This patch supports the multiple IORESOURCE_MEM resources for one pin-bank. In the pre-existing Exynos series, the registers of the gpio bank are included in the one memory map. But, some gpio bank need to support the one more memory map (IORESOURCE_MEM) because the registers of gpio bank are separated into the different memory map. For example, The both ALIVE and IMEM domain have the different memory base address. The GFP[1-5] of exynos5433 are composed as following: - ALIVE domain : WEINT_* registers - IMEM domain : CON/DAT/PUD/DRV/CONPDN/PUDPDN register Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Tomasz Figa <tomasz.figa@gmail.com> Cc: Krzysztof Kozlowski <krzk@kernel.org> Cc: Sylwester Nawrocki <s.nawrocki@samsung.com> Cc: Kukjin Kim <kgene@kernel.org> Cc: linux-gpio@vger.kernel.org Suggested-by:
Tomasz Figa <tomasz.figa@gmail.com> Signed-off-by:
Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by:
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- 14 Nov, 2016 2 commits
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Phil Elwell authored
When dynamically unloading overlays, it is important that freed pins are restored to being inputs to prevent functions from being enabled in multiple places at once. Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
Phil Elwell <phil@raspberrypi.org> Acked-by:
Eric Anholt <eric@anholt.net> Signed-off-by:
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Phil Elwell authored
Contrary to the documentation, the BCM2835 GPIO controller actually has four interrupt lines - one each for the three IRQ groups and one common. Confusingly, the GPIO interrupt groups don't correspond directly with the GPIO control banks. Instead, GPIOs 0-27 generate IRQ GPIO0, 28-45 IRQ GPIO1 and 46-53 IRQ GPIO2. Awkwardly, the GPIOs for IRQ GPIO1 straddle two 32-entry GPIO banks, so split out a function to process the interrupts for a single GPIO bank. Cc: Stefan Wahren <stefan.wahren@i2se.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by:
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- 11 Nov, 2016 2 commits
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Axel Haslam authored
The pcs_parse_bits_in_pinctrl_entry function should search for the "pinctrl-single,bits" and not "pinctrl-single,pins" Signed-off-by:
Axel Haslam <ahaslam@baylibre.com> Acked-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Axel Haslam authored
pinctrl_count_index_with_args returns -ENOENT not -EINVAL. The return check would pass, and we would try to kzalloc with a negative error size throwing a warning. Instead of checking for -EINVAL specifically, lets check for any error and avoid negative size allocations. Signed-off-by:
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- 08 Nov, 2016 19 commits
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Heinrich Schuchardt authored
for_each_property_of_node(pins, pp) checks that pp is not NULL. So there is no need to check it inside the loop. Signed-off-by:
Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by:
Patrice Chotard <patrice.chotard@st.com> Signed-off-by:
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Heinrich Schuchardt authored
function is defined as unsigned int. So we need %u to print it. Signed-off-by:
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Linus Walleij authored
Merge tag 'sh-pfc-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel pinctrl: sh-pfc: Updates for v4.10 - I2C and DRIF pin groups for R-Car M3-W, - Bug fixes for SDHI2/3 on R-Car M3-W.
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Linus Walleij authored
Include <linux/gpio/driver.h> rather than <linux/gpio.h> Drop <linux/pinctrl/machine.h>. Cc: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: -
Andrey Smirnov authored
Tested-by:
Neil Armstrong <narmstrong@baylibre.com> Acked-by:
Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by:
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Andrey Smirnov authored
Tested-by:
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Andrey Smirnov authored
Althought the function passed as a "handler" during GPIO chip instantiation is not going to ever be called, specifying handle_edge_irq there makes for a rather confusing read, both because no "ack" callback in specified for irqchip and because there's no acking action is necessary. Specify handle_bad_irq instead a make a note of the situation. This commit should be a no-op behaviour wise. Tested-by:
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Andrey Smirnov authored
Make use of for_each_set_bit macro and reduce boilerplate code. Tested-by:
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Andrey Smirnov authored
Move actual code that configures oscio pin into a separate function and use it instead of calling sx150x_gpio_set to avoid calling sx150x_pin_is_oscio twice and correctly propagte error code in sx150x_gpio_direction_output. Tested-by:
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Andrey Smirnov authored
Gpiochip and irqchip aspects of this driver do not access any shared registers on the chip itself and atomicity of various regmap operations is ensured by that API's implementation, so there doesn't seem to be a reason to hold the lock in as many places as it is held now. Tested-by:
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Andrey Smirnov authored
The difference between 8 and 16 pin GPIO expanders can be accomodated by the means of regmap API without resorting to using driver-specific read/write accessors. This change, IMHO, brings the following benefits: - Replaces driver's idiosyncratic way of dealing with mult-register fields with regmap API, which, hopefuly, makes the code a bit easier for a new reader to understand - Removes various multi-read for-loop register read logic from various places in the code and puts it in a signle place - Removes ad-hoc IRQ register caching code in sx150x_irq_bus_sync_unlock, since that functionality is provided by regmap Besided aforementioned benefits this change also implements necessary RegSense byte swap necessary for SX1503 and SX1506 variants of the chip. Tested-by:
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Andrey Smirnov authored
To allow for future code simplification Tested-by:
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Andrey Smirnov authored
For Sx1504/5/6 only SX1506 has RegAdvanced, so put some code in place to account for that. Tested-by:
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Andrey Smirnov authored
Move the code configuring explicit IRQ acking into a standalone function to declutter sx150x_init_hw a bit and make that code somewhat less repetitious. Tested-by:
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Andrey Smirnov authored
According to the datasheet for SX1504/5/6, RegAdvanced's "Autoclear NINT" bit that turns the feature when set and disables it when cleared, so writing 0x04 to the register will have the opposite from desirable effect. Tested-by:
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Andrey Smirnov authored
Tested-by:
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Andrey Smirnov authored
Signed-off-by:
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Andrey Smirnov authored
Tested-by:
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Andrey Smirnov authored
Add proper device specific information to of_device_id table of the driver and add code to match against and fetch said data from it. Signed-off-by:
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- 07 Nov, 2016 1 commit
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Geert Uytterhoeven authored
Fix off-by-one (row and/or register) errors in links to Peripheral Function Select Register bitfields from GPIO/Peripheral Function Select Register 4 macros for SDHI2 and SDHI3 pins. Based on rev. 0.52E of the R-Car Gen3 User's Manual. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Tested-by:
Simon Horman <horms+renesas@verge.net.au>
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- 04 Nov, 2016 9 commits
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Michael Scott authored
Initial pinctrl driver for QCOM msm8994 platforms. In order to continue the initial board support for QCOM msm8994/msm8992 presented in patches from Jeremy McNicoll <jeremymc@redhat.com>, let's put a proper pinctrl driver in place. Currently, the DT for these platforms uses the msm8x74 pinctrl driver to enable basic UART. Beyond the first few pins the rest are different enough to justify it's own driver. Note: This driver is also used by QCOM's msm8992 platform as it's TLM block is the same. - Initial formatting and style was taken from the msm8x74 pinctrl driver added by Björn Andersson <bjorn.andersson@linaro.org> - Data was then adjusted per QCOM MSM8994v2 documentation for Top Level Multiplexing - Bindings documentation was based on qcom,msm8996-pinctrl.txt by Joonwoo Park <joonwoop@codeaurora.org> and then modified for msm8994 content Signed-off-by:
Michael Scott <michael.scott@linaro.org> Tested-by:
Jeremy McNicoll <jeremymc@redhat.com> Acked-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Paul Gortmaker authored
None of the Kconfigs for any of these drivers are tristate, meaning that they currently are not being built as a module by anyone. Lets remove the modular code that is essentially orphaned, so that when reading the drivers there is no doubt they are builtin-only. All drivers get essentially the same change, so they are handled in batch. Changes are (1) use builtin_platform_driver, (2) use init.h header (3) delete module_exit related code, (4) delete MODULE_DEVICE_TABLE, and (5) delete MODULE_LICENCE/MODULE_AUTHOR and associated tags. Since module_platform_driver() uses the same init level priority as builtin_platform_driver() the init ordering remains unchanged with this commit. Also note that MODULE_DEVICE_TABLE is a no-op for non-modular code. We do delete the MODULE_LICENSE etc. tags since all that information is already contained at the top of each file in the comments. Cc: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: Chen-Yu Tsai <wens@csie.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Hongzhou Yang <hongzhou.yang@mediatek.com> Cc: Fabian Frederick <fabf@skynet.be> Cc: Maxime Coquelin <maxime.coquelin@st.com> Cc: Vishnu Patekar <vishnupatekar0510@gmail.com> Cc: Mylene Josserand <mylene.josserand@free-electrons.com> Cc: linux-gpio@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by:
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Neil Armstrong authored
Add support for the Amlogic Meson GXL SoC, this is a partially complete definition only based on the Amlogic Vendor tree. This definition differs a lot from the GXBB and needs a separate entry. Acked-by:
Kevin Hilman <khilman@baylibre.com> Signed-off-by:
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Tony Lindgren authored
We can now use generic parser and keep things compatible with the old binding. Signed-off-by:
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Tony Lindgren authored
We can now use generic parser. To support the legacy binding without #pinctrl-cells, add pcs_quirk_missing_pinctrl_cells() and warn about missing #pinctrl-cells. Let's also update the documentation for struct pcs_soc_data while at it as that seems to be out of date. Signed-off-by:
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Tony Lindgren authored
Introduce #pinctrl-cells helper binding and generic helper functions pinctrl_count_index_with_args() and pinctrl_parse_index_with_args(). Acked-by:
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Stefan Wahren authored
Since the BCM2835 datasheet doesn't exactly specify the set-up time for the GPIO Pull-up/down Clock Registers there was an assumption of 150 cycles at a clock rate of 1 MHz. During a discussion [1] in the Raspberry Pi forum it turns out that clock rate refers to the VPU which has a rate of 250 MHz. So we can reduce the delay to a sensible value and update the comment above. I tested this optimization with a Raspberry Pi B and a multimeter. [1] - https://www.raspberrypi.org/forums/viewtopic.php?f=72&t=163352Signed-off-by:
Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by:
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Mika Westerberg authored
Printing the prefix does not provide any additional information. In addition this makes the output look more consistent with pinctrl-intel.c. Signed-off-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Jason Gunthorpe authored
The hardware supports a 16 and 8 bit wide NAND bus, let users pick either. Signed-off-by:
Jason Gunthorpe <jgunthorpe@obsidianresearch.com> Acked-by:
Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by:
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- 31 Oct, 2016 1 commit
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Boris BREZILLON authored
Add support for pin output control through the pinctrl config: - support enabling/disabling output on a given pin - support output level setting (high or low) Signed-off-by:
Boris BREZILLON <b.brezillon@overkiz.com> Acked-by:
Nicolas Ferre <nicolas.ferre@atmel.com> Signed-off-by:
Wenyou Yang <wenyou.yang@atmel.com> Signed-off-by:
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