- 19 Feb, 2018 40 commits
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Christian König authored
Stuffing the PASID mapping into the VM flush isn't flexible enough since the PASID mapping changes not as often as we need a VM flush. v2: add missing use of gmc_v7_0_emit_pasid_mapping Signed-off-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Leo (Sunpeng) Li authored
Previously, the number of software segmets per region was reduced to 16. This needs to be reflected in the sampling distance (increment) used when translating to the hardware format. Signed-off-by:
Leo (Sunpeng) Li <sunpeng.li@amd.com> Reviewed-by:
Krunoslav Kovac <Krunoslav.Kovac@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
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Vitaly Prosyak authored
Some refactoring and optimizations in color module. Added de gamma 2.2 & 2.4, also re gamma 2.2. Added interface for diagnostic for de gamma & de pq. Signed-off-by:
Vitaly Prosyak <vitaly.prosyak@amd.com> Reviewed-by:
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Harry Wentland authored
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Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Acked-by:
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Eric Yang authored
Add basic logging for DPCD access. Does not print by default. Currently only prints first byte of the data accessed. Technical debt: Need to make it so that the entire data block accessed is printed. Also need to log address space that's not DPCD. Signed-off-by:
Eric Yang <Eric.Yang2@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
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Tao authored
Brightness couldn't change when booting up in DC mode. It was because "psr_enabled" flag was not set to true before setting vsc packet revision, causing packet rev setup was skipped. Now instead of checking the psr flag, it checks if the DPCD_REV >= 1.2 and set the vsc packet revision. Signed-off-by:
Tao <xtao@amd.com> Reviewed-by:
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Anthony Koo authored
Signed-off-by:
Anthony Koo <Anthony.Koo@amd.com> Reviewed-by:
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Harry Wentland authored
Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Eric Yang authored
We have an mst dock firmware that will emulate an EDID with bad checksum. v2: Tread -> Treat Signed-off-by:
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Ken Chalmers authored
Identical to the two entries above them. Signed-off-by:
Ken Chalmers <ken.chalmers@amd.com> Reviewed-by:
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Roman Li authored
Previously, FBC dynamic allocation relied on connector modes populated during dm init. This is only the case if DRM_FBDEV_EMULATION config flag is enabled. Moving fbc allocation from dm_late_init() to amdgpu_dm_connector_get_modes() where actual modes init happens. Signed-off-by:
Roman Li <Roman.Li@amd.com> Reviewed-by:
Shirish Shankarappa <Shirish.S@amd.com> Acked-by:
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John Barberiz authored
HDMI HPD's generic solution makes the monitor patch code unnecessary so anything related has been removed. Signed-off-by:
John Barberiz <jbarberi@amd.com> Reviewed-by:
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Leo (Sunpeng) Li authored
Skipping the first frame will prevent uncoooked values most of the time. However, in some unlikely cases, the second frame will be uncooked as well. Signed-off-by:
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Leo (Sunpeng) Li authored
Implement CRC for DCE8. Registers remain the same, so call DCE110 code directly. Signed-off-by:
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Leo (Sunpeng) Li authored
Clear up the logic, and enable programming truncation as a bit reduction mode. Signed-off-by:
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Leo (Sunpeng) Li authored
When user-mode is using 8bpc, the hardware represents it internally using a higher bit depth. This causes problems when comparing CRCs for color managment tests. We need to disable dithering as well, since it makes CRC values non-deterministic. It's easy to see why dithering needs to be disabled, The reason why truncation also needs to be enabled is better described with an example. Consider the folowing which tests the color transform matrix (CTM): Expected CRC = FB_A -> Degamma (Bypassed) -> CTM (Bypassed) | v Obtain CRC <- Regamma(Bypassed) Actual CRC = FB_B -> Degamma (Bypassed) -> CTM (0.5*Identity) | v Obtain CRC <- Regamma(Bypassed) FB_A contains a solid red color at half intensity (127 @ 8bpc) FB_B contains a solid red color at full intensity (255 @ 8bpc) We expect that Expected CRC = Actual CRC, but that's not the case. When the CTM is applied, the output is at half intensity, but also at a higher bit depth within hardware. i.e. 255/2 = 127.5: not representable in 8bpc, but can be at 10bpc. This causes the two CRC's to be different. The solution is to truncate the output bit depth to the same as input when enabling CRC capture. Since Linux only supports 8bpc, hard code that for now. Signed-off-by: -
Leo (Sunpeng) Li authored
We will need this to disable dither for CRC capture. Signed-off-by:
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Leo (Sunpeng) Li authored
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Leo (Sunpeng) Li authored
Hookup new color management functions into amdgpu_dm: - Notify DRM that we support CRTC color management during CRTC init - Call color management functions within atomic check to update dc states in preparation for a commit Signed-off-by:
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Leo (Sunpeng) Li authored
Implement color management functionalities within amdgpu_dm_color, and expose functions within amdgpu_dm.h. Signed-off-by:
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Leo (Sunpeng) Li authored
Also guard includes that we don't need. Signed-off-by:
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Leo (Sunpeng) Li authored
The MAX_LOW_POINT macro should reflect the maximum low point within hardware. Otherwise, sampling for the hardware points from the output transfer function (OTF) will be incorrect. Also, fix usage of MAX_LOW_POINT accordingly. Signed-off-by:
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Harry Wentland authored
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Harry Wentland authored
Both functions are the same Signed-off-by:
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Harry Wentland authored
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Yongqiang Sun authored
This path fixed specific eDP panel cold boot black screen due to unnecessary enable link. Change: In case of boot up with eDP, if OS is going to set mode on eDP, keep eDP light up, do not disable and reset corresponding HW. This change may affect dce asics and S3/S4 Resume with multi-monitor. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Tony Cheng authored
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Dmytro Laktyushkin authored
Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
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Martin Tsai authored
Signed-off-by:
Martin Tsai <martin.tsai@amd.com> Reviewed-by:
Charlene Liu <Charlene.Liu@amd.com> Acked-by:
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Harry Wentland authored
These should only be non-0 if big hammer w/a is implemented. Currently DC doesn't implement it, so leave them 0. Signed-off-by:
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Charlene Liu authored
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Tony Cheng authored
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Charlene Liu authored
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Hersen Wu authored
[Description] For MST, DC already notify MST sink for MST mode, DC stll check DP SINK DPCD register to see if MST enabled. DP RX firmware may not handle this properly. Signed-off-by:
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John Barberiz authored
- Disabled HPD filter and used HPD software timer instead - Allows DM to disable HPD filtering Signed-off-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Harry Wentland authored
v2: Use NULL and reverse christmas tree ordering Signed-off-by:
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Mikita Lipski authored
amdgpu_dm_display_resume is now called from dm_resume to unify DAL resume call into a single function call There is no more need to separately call 2 resume functions for DM. Initially they were separated to resume display state after cursor is pinned. But because there is no longer any corruption with the cursor - the calls can be merged into one function hook. Signed-off-by:
Mikita Lipski <mikita.lipski@amd.com> Reviewed-by:
Andrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by:
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Mikita Lipski authored
Inside amdgpu_gtt_mgr_fini add a missing lock to maintain locking balance Signed-off-by:
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Christian König authored
Start to use amdgpu_bo_create_reserved v2. v2: Fix missing pointer init to NULL. Remove extra new lines. Signed-off-by:
Leo Liu <leo.liu@amd.com> Signed-off-by:
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Christian König authored
We didn't synced the BO after validating it. Also sart to use amdgpu_bo_create_reserved to simplify things. Signed-off-by:
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