- 09 Oct, 2019 9 commits
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Paul Burton authored
CMDLINE, CMDLINE_BOOL & CMDLINE_FORCE all explicitly specify default values that are the same as the default value for their respective types anyway (ie. n for booleans, and the empty string for strings). Remove the redundant defaults. Signed-off-by:
Paul Burton <paul.burton@mips.com> Reviewed-by:
Philippe Mathieu-Daudé <f4bug@amsat.org> Cc: linux-mips@vger.kernel.org
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Thomas Bogendoerfer authored
EARLY_PRINTK uses ArcWrite (via prom_putchar) on IP22/28, which needs to not mess up PROMs data structures. ARC PROM gives out a list of memory chunks, which are used and which are free. This fixes the problem of not working early printk. By using XKPHYS spaces more than 256MB memory on Indigo2 R4k machines is working now, too. Signed-off-by:
Thomas Bogendoerfer <tbogendoerfer@suse.de> Signed-off-by:
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Thomas Bogendoerfer authored
IP22 started at physical 0x08000000. To avoid wasting memory for page structs set PHYS_OFFSET. Signed-off-by:
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Thomas Bogendoerfer authored
Pointer arguments for 32bit ARC PROMs must reside in CKSEG0/1. While the initial stack resides in CKSEG0 the first kernel thread stack is already placed at a XKPHYS address, which ARC32 can't handle. The workaround here is to use static variables, which are placed into BSS and linked to a CKSEG0 address. Signed-off-by:
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Thomas Bogendoerfer authored
Instead of having a default y option with depends simply select options for the platforms where they are needed. Signed-off-by:
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Thomas Bogendoerfer authored
When using a 64bit kernel with generic spaces setup stack is also placed in XKPYHS, which the 32bit PROM can't handle. By using call_o32 for ARC_CALLs a stack placed in KSEG0 is used when calling PROM. Signed-off-by:
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Thomas Bogendoerfer authored
Current kernel uses only a few ARC calls. Drop all unused ARC functions. Signed-off-by:
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Paul Burton authored
We have assembly implementations of strcpy(), strncpy(), strcmp() & strncmp() which: - Are simple byte-at-a-time loops with no particular optimizations. As a comment in the code describes, they're "rather naive". - Offer no clear performance advantage over the generic C implementations - in microbenchmarks performed by Alexander Lobakin the asm functions sometimes win & sometimes lose, but generally not by large margins in either direction. - Don't support 64-bit kernels, where we already make use of the generic C implementations. - Tend to bloat kernel code size due to inlining. - Don't support CONFIG_FORTIFY_SOURCE. - Won't support nanoMIPS without rework. For all of these reasons, delete the asm implementations & make use of the generic C implementations for 32-bit kernels just like we already do for 64-bit kernels. Signed-off-by:
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Paul Burton authored
Currently we have a lot of duplication in asm/r4kcache.h to handle manually unrolling loops of cache ops for various line sizes, and we have to explicitly handle the difference in cache op immediate width between MIPSr6 & earlier ISA revisions with further duplication. Introduce an unroll() macro in asm/unroll.h which expands to a switch statement which is used to call a function or expand a preprocessor macro a compile-time constant number of times in a row - effectively explicitly unrolling a loop. We make use of this here to remove the cache op duplication & will use it further in later patches. A nice side effect of this is that calculating the cache op offset immediate is now the compiler's responsibility, so we're no longer sensitive to the width change of that immediate in MIPSr6 & will be similarly agnostic to immediate width in any future supported ISA. Signed-off-by:
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- 08 Oct, 2019 1 commit
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Tiezhu Yang authored
Fix the following checkpatch errors: $ ./scripts/checkpatch.pl --no-tree -f arch/mips/generic/init.c ERROR: Use of const init definition must use __initconst #23: FILE: arch/mips/generic/init.c:23: +static __initdata const void *fdt; ERROR: Use of const init definition must use __initconst #24: FILE: arch/mips/generic/init.c:24: +static __initdata const struct mips_machine *mach; ERROR: Use of const init definition must use __initconst #25: FILE: arch/mips/generic/init.c:25: +static __initdata const void *mach_match_data; Fixes: eed0eabd ("MIPS: generic: Introduce generic DT-based board support") Signed-off-by:
Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by:
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- 07 Oct, 2019 30 commits
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Paul Burton authored
Commit 3c1d3f09 ("MIPS: futex: Emit Loongson3 sync workarounds within asm") inadvertently removed the newlines following __WEAK_LLSC_MB, which causes build failures for configurations in which __WEAK_LLSC_MB expands to a sync instruction: {standard input}: Assembler messages: {standard input}:9346: Error: symbol `sync3' is already defined {standard input}:9380: Error: symbol `sync3' is already defined ... Fix this by restoring the newlines to separate the sync instruction from anything following it (such as the 3: label), preventing inadvertent concatenation. Signed-off-by:
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Aurabindo Jayamohanan authored
{save,restore}_dsp() internally checks if the cpu has dsp support. Therefore, explicit check is not required before calling them in {save,restore}_processor_state() Signed-off-by:Aurabindo Jayamohanan <mail@aurabindo.in> Signed-off-by:
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Thomas Bogendoerfer authored
IOC3 chips in SGI system are conntected to a bridge ASIC, which has a 1-wire prom attached with part number information. This changeset uses this information to create PCI subsystem information, which the MFD driver uses for further platform device setup. Signed-off-by:
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Thomas Bogendoerfer authored
nvmem_device_find provides a way to search for nvmem devices with the help of a match function simlair to bus_find_device. Reviewed-by:
Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Acked-by:
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Alexandre GRIVEAUX authored
Adding leds and related triggers. Signed-off-by:
Alexandre GRIVEAUX <agriveaux@deutnet.info> Signed-off-by:
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Alexandre GRIVEAUX authored
Add IW8103 Wifi + bluetooth module to device tree and related power domain. Signed-off-by:
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Alexandre GRIVEAUX authored
Adding missing I2C nodes and some peripheral: - PMU - RTC Signed-off-by:
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Alexandre GRIVEAUX authored
Add the devicetree nodes for the I2C core of the JZ4780 SoC, disabled by default. Signed-off-by:
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Dmitry Korotin authored
FORTIFY_SOURCE detects various overflows at compile and run time. (6974f0c4 ("include/linux/string.h: add the option of fortified string.h functions) ARCH_HAS_FORTIFY_SOURCE means that the architecture can be built and run with CONFIG_FORTIFY_SOURCE. Since mips can be built and run with that flag, select ARCH_HAS_FORTIFY_SOURCE as default. Signed-off-by:
Dmitry Korotin <dkorotin@wavecomp.com> Signed-off-by:
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Huacai Chen authored
CSR IPI and legacy MMIO use the same infrastructure, but CSR IPI is faster than legacy MMIO IPI. This patch enable CSR IPI if possible (except for MailBox, because CSR IPI is too complicated for MailBox). Signed-off-by:
Huacai Chen <chenhc@lemote.com> Signed-off-by:
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Huacai Chen authored
All Loongson-3 CPU family: Code-name Brand-name PRId Loongson-3A R1 Loongson-3A1000 0x6305 Loongson-3A R2 Loongson-3A2000 0x6308 Loongson-3A R2.1 Loongson-3A2000 0x630c Loongson-3A R3 Loongson-3A3000 0x6309 Loongson-3A R3.1 Loongson-3A3000 0x630d Loongson-3A R4 Loongson-3A4000 0xc000 Loongson-3B R1 Loongson-3B1000 0x6306 Loongson-3B R2 Loongson-3B1500 0x6307 Features of R4 revision of Loongson-3A: - All R2/R3 features, including SFB, V-Cache, FTLB, RIXI, DSP, etc. - Support variable ASID bits. - Support MSA and VZ extensions. - Support CPUCFG (CPU config) and CSR (Control and Status Register) extensions. - 64 entries of VTLB (classic TLB), 2048 entries of FTLB (8-way set-associative). Now 64-bit Loongson processors has three types of PRID.IMP: 0x6300 is the classic one so we call it PRID_IMP_LOONGSON_64C (e.g., Loongson-2E/ 2F/3A1000/3B1000/3B1500/3A2000/3A3000), 0x6100 is for some processors which has reduced capabilities so we call it PRID_IMP_LOONGSON_64R (e.g., Loongson-2K), 0xc000 is supposed to cover all new processors in general (e.g., Loongson-3A4000+) so we call it PRID_IMP_LOONGSON_64G. Signed-off-by:Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by:
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Huacai Chen authored
Loongson-3A R4+ (Loongson-3A4000 and newer) has CPUCFG (CPU config) and CSR (Control and Status Register) extensions. This patch add read/write functionalities for them. Signed-off-by:
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Mike Rapoport authored
The memory initialization of SGI-IP27 is already half-way to support SPARSEMEM. It only had free_bootmem_with_active_regions() left-overs interfering with sparse_memory_present_with_active_regions(). Replace these calls with simpler memblocks_present() call in prom_meminit() and adjust arch/mips/Kconfig to enable SPARSEMEM and SPARSEMEM_EXTREME for SGI-IP27. Co-developed-by:
Mike Rapoport <rppt@linux.ibm.com> Signed-off-by:
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Paul Burton authored
When Loongson3 LL/SC errata workarounds are enabled (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) run a tool to scan through the compiled kernel & ensure that the workaround is applied correctly. That is, ensure that: - Every LL or LLD instruction is preceded by a sync instruction. - Any branches from within an LL/SC loop to outside of that loop target a sync instruction. Reasoning for these conditions can be found by reading the comment above the definition of __SYNC_loongson3_war in arch/mips/include/asm/sync.h. This tool will help ensure that we don't inadvertently introduce code paths that miss the required workarounds. Signed-off-by: -
Paul Burton authored
In ejtag_debug_handler() we must reload the address of ejtag_debug_buffer_spinlock if an sc fails, since the address in k0 will have been clobbered by the result of the sc instruction. In the case where we simply load a non-zero value (ie. there's contention for the lock) the address will not be clobbered & we can simply branch back to repeat the load from memory without reloading the address into k0. The primary motivation for this change is that it moves the target of the bnez instruction to an instruction within the LL/SC loop (the LL itself), which we know contains no other memory accesses & therefore isn't affected by Loongson3 LL/SC errata. Signed-off-by: -
Paul Burton authored
In ejtag_debug_handler we use LL & SC instructions to acquire & release an open-coded spinlock. For Loongson3 systems affected by LL/SC errata this requires that we insert a sync instruction prior to the LL in order to ensure correct behavior of the LL/SC loop. Signed-off-by: -
Paul Burton authored
Loongson3 systems with CONFIG_CPU_LOONGSON3_WORKAROUNDS enabled already emit a full completion barrier as part of the inline assembly containing LL/SC loops for atomic operations. As such the barrier emitted by __smp_mb__before_atomic() is redundant, and we can remove it. Signed-off-by: -
Paul Burton authored
The loongson_llsc_mb() macro is no longer used - instead barriers are emitted as part of inline asm using the __SYNC() macro. Remove the now-defunct loongson_llsc_mb() macro. Signed-off-by: -
Paul Burton authored
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: -
Paul Burton authored
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: -
Paul Burton authored
When building a kernel configured to support Loongson3 LL/SC workarounds (ie. CONFIG_CPU_LOONGSON3_WORKAROUNDS=y) the inline assembly in __xchg_asm() & __cmpxchg_asm() already emits completion barriers, and as such we don't need to emit extra barriers from the xchg() or cmpxchg() macros. Add compile-time constant checks causing us to omit the redundant memory barriers. Signed-off-by: -
Paul Burton authored
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: -
Paul Burton authored
Use smp_mb__before_atomic() rather than smp_mb__before_llsc() in test_and_set_bit(), test_and_clear_bit() & test_and_change_bit(). The _atomic() versions make semantic sense in these cases, and will allow a later patch to omit redundant barriers for Loongson3 systems that already include a barrier within __test_bit_op(). Signed-off-by: -
Paul Burton authored
Generate the sync instructions required to workaround Loongson3 LL/SC errata within inline asm blocks, which feels a little safer than doing it from C where strictly speaking the compiler would be well within its rights to insert a memory access between the separate asm statements we previously had, containing sync & ll instructions respectively. Signed-off-by: -
Paul Burton authored
Rather than using custom SZLONG_LOG & SZLONG_MASK macros to shift & mask a bit index to form word & bit offsets respectively, make use of the standard BIT_WORD() & BITS_PER_LONG macros for the same purpose. volatile is added to the definition of pointers to the long-sized word we'll operate on, in order to prevent the compiler complaining that we cast away the volatile qualifier of the addr argument. This should have no effect on generated code, which in the LL/SC case is inline asm anyway & in the non-LLSC case access is constrained by compiler barriers provided by raw_local_irq_{save,restore}(). Signed-off-by: -
Paul Burton authored
Introduce __bit_op() & __test_bit_op() macros which abstract away the implementation of LL/SC loops. This cuts down on a lot of duplicate boilerplate code, and also allows R10000_LLSC_WAR to be handled outside of the individual bitop functions. Signed-off-by: -
Paul Burton authored
The IRQ-disabling non-LLSC fallbacks for bitops on UP systems already return a zero or one, so there's no need to perform another comparison against zero. Move these comparisons into the LLSC paths to avoid the redundant work. Signed-off-by: -
Paul Burton authored
Use the BIT() macro in asm/bitops.h rather than open-coding its equivalent. Signed-off-by: -
Paul Burton authored
The logical operations or & xor used in the test_and_set_bit_lock(), test_and_clear_bit() & test_and_change_bit() functions currently force the value 1<<bit to be placed in a register. If the bit is compile-time constant & fits within the immediate field of an or/xor instruction (ie. 16 bits) then we can make use of the ori/xori instruction variants & avoid the use of an extra register. Add the extra "i" constraints in order to allow use of these immediate encodings. Signed-off-by: -
Paul Burton authored
The only difference between test_and_set_bit() & test_and_set_bit_lock() is memory ordering barrier semantics - the former provides a full barrier whilst the latter only provides acquire semantics. We can therefore implement test_and_set_bit() in terms of test_and_set_bit_lock() with the addition of the extra memory barrier. Do this in order to avoid duplicating logic. Signed-off-by:
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