- 25 Feb, 2020 40 commits
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Yu-ting Shen authored
[Why] when changing display clock, SMU need to use power up DFS and use DENTIST to ramp DFS DID to switch target frequency before switching back to bypass. [How] fixed the minimum display clock to 100MHz, it's W/A the same with PCO. Signed-off-by:
Yu-ting Shen <Yu-ting.Shen@amd.com> Reviewed-by:
Tony Cheng <Tony.Cheng@amd.com> Acked-by:
Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by:
Harry Wentland <harry.wentland@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Jaehyun Chung authored
[Why] System will crash when trying to access local sink in core_link_enable_stream in MST case. [How] Access patches directly from stream. Signed-off-by:
Jaehyun Chung <jaehyun.chung@amd.com> Reviewed-by:
Aric Cyr <Aric.Cyr@amd.com> Reviewed-by:
Ashley Thomas <Ashley.Thomas2@amd.com> Acked-by:
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George Shen authored
[Why] Underflow sometimes occurs during transition into MPO with stutter enabled. [How] When transitioning into MPO, disable stutter. Re-enable stutter within one frame. Signed-off-by:
George Shen <george.shen@amd.com> Signed-off-by:
Eric Yang <eric.yang2@amd.com> Acked-by:
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Sung Lee authored
[WHY] Currently clock table struct is very far down in the bounding box struct making it hard to find while debugging, especially when using the dal3dbgext. [HOW] Move it up so it is the first struct defined, and therefore much easier to find and access. Signed-off-by:
Sung Lee <sung.lee@amd.com> Reviewed-by:
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Yongqiang Sun authored
[Why] In some display configuration like 1080P monitor playing a 1080P video, if user use ALT+F4 to exit Movie and TV, there is a chance clocks are same only water mark changed. Current clock optimization machanism will result in water mark keeps high after exit Movie and TV app. [How] Return if watermark need to be optimized when doing program watermark, perform the optimization after. Signed-off-by:
Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by:
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Dmytro Laktyushkin authored
Need to assign surface size rather than viewport size for surface size dml variable. Signed-off-by:
Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by:
Eric Bernstein <Eric.Bernstein@amd.com> Acked-by:
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Alvin Lee authored
[Why] We need to update TTU properly if DRAMClockChangeWatermark changes. If TTU < DRAMClockChangeWatermark, we pstate won't be allowed and we will hang in some PSR cases. [How] Update TTU if DramClockChangeWatermark value increases (only if TTU was dependent on the watermark value on the DRAMClockChangeWatermark value in the first place). Signed-off-by:
Alvin Lee <alvin.lee2@amd.com> Reviewed-by:
Jun Lei <Jun.Lei@amd.com> Acked-by:
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Michael Strauss authored
[WHY] RV2 and variants are indistinguishable by hw internal rev alone, need to be distinguishable in order to correctly set max vlevel. Previous detection change incorrectly checked for hw internal rev. [HOW] Use pci revision to check if RV2 or low power variant Correct a few overlapping ASICREV range checks Signed-off-by:
Michael Strauss <michael.strauss@amd.com> Reviewed-by:
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Wyatt Wood authored
[Why] We want to be able to enable PSR on DMCUB, and fallback to DMCU when necessary. [How] Add infrastructure to enable and disable PSR on DMCUB. Signed-off-by:
Wyatt Wood <wyatt.wood@amd.com> Reviewed-by:
Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Dmytro Laktyushkin authored
Signed-off-by:
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Dmytro Laktyushkin authored
Update dcn20_populate_dml_pipes_from_context to correctly handle odm when no surface is provided. Signed-off-by:
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Peikang Zhang authored
[Why] DalMPVisualConfirm does not support FreeSync 2 ARGB2101010 which causes black visual confirm bar when playing HDR video on FreeSync 2 display in full screen mode [How] Added pink color for DalMPVisualConfirm on FreeSync 2 ARGB2101010 surface Signed-off-by:
Peikang Zhang <peikang.zhang@amd.com> Reviewed-by:
Anthony Koo <Anthony.Koo@amd.com> Acked-by:
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Martin Leung authored
[Why] Previously implemented early_cr_pattern was link level but the whole asic should be affected. [How] - change old link flag to dc level - new bit in dc->work_arounds set by DM Signed-off-by:
Martin Leung <martin.leung@amd.com> Reviewed-by:
Joshua Aberback <Joshua.Aberback@amd.com> Acked-by:
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Jaehyun Chung authored
[Why] Some displays clear ignore MSA bit on mode change, which cause blackscreen when programming variable vtotals. Ignore MSA bit needs programming needs to be delayed or re-set to be retained. [How] Create patch to delay programming ignore MSA bit after unblanking stream. Signed-off-by:
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David Galiffi authored
[Why] A software workaround is required for all vendor-built cards on platform. [How] When performing DP link training, we must send TPS1 before DPCD:100h is written with the proper bit rate value. This change must be applies in ALL cases when LT happens. Signed-off-by:
David Galiffi <David.Galiffi@amd.com> Reviewed-by:
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Sung Lee authored
[WHY] Not programming dto with same values causes test failures in DCN2 diags DPP tests. [HOW] This reverts commit 1b53e733. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] Firmware state helps to debug sequence issues and hangs for DMCUB commands and we don't have an easy mechanism to dump it from the driver. [How] Add a debugfs entry to dump the current firmware state. Example usage: cat /sys/kernel/debug/dri/0/amdgpu_dm_dmub_fw_state Signed-off-by:
Hersen Wu <hersenxs.wu@amd.com> Acked-by:
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Vladimir Stempen authored
[Why] Currently DAL programs negative slope for the last point of output transfer function curve. [How] Applying a check for the last PWL point for RGB values not to be smaller than previous. If smaller, initialize the last point values to a sum of previous PWL value and previous PWL delta; Signed-off-by:
Vladimir Stempen <vladimir.stempen@amd.com> Reviewed-by:
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Anthony Koo authored
[Why] There are some structures and functions meant only to be used in the scope of that single rn_clk_mgr c file. [How] Make structs and funcs static if only meant to be used within rn_clk_mgr Signed-off-by:
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Anthony Koo authored
[Why] Make panel backlight and power on/off functions into hardware specific function pointers [How] Add function pointers for panel related hw functions - is_panel_powered_on - is_panel_backlight_on Signed-off-by:
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Bhawanpreet Lakha authored
when the rxstatus split was done the index was incorrect. This lead to HDMI repeater authentication failure for HDCP2.X So fix it Fixes: 30216900 ("drm/amd/display: split rxstatus for hdmi and dp") Signed-off-by:
Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by:
Wenjing Liu <Wenjing.Liu@amd.com> Acked-by:
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Aric Cyr authored
Signed-off-by:
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Aric Cyr authored
[Why] When calculating nominal refresh rates, don't round. Only the VSIF needs to be rounded. [How] Revert rounding change for nominal and just round when forming the FreeSync VSIF. Signed-off-by:
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Peikang Zhang authored
[Why] Unused VMIDs were not evicted correctly [How] 1. evict_vmids() logic was fixed; 2. Added boundary check for add_ptb_to_table() and clear_entry_from_vmid_table() to avoid crash caused by array out of boundary; 3. For mod_vmid_get_for_ptb(), vimd is changed from unsigned to signed due to vimd is signed. Signed-off-by:
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Samson Tam authored
[Why] Add optimization to allow pstate change support when all displays are off in DCN2. [How] Add clk_mgr_helper_get_active_plane_cnt() to sum plane_count for all valid stream_status[]. If plane_count is 0, then there are no active or virtual streams present. Use plane_count == 0 as extra condition to enable p_state_change_support in dcn2_update_clocks(). Signed-off-by:
Samson Tam <Samson.Tam@amd.com> Reviewed-by:
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Roman Li authored
[Why] We need DMCU for features like PSR and ABM. [How] Add path to dmcu firmware binary and load it for Navi12. Signed-off-by:
Roman Li <roman.li@amd.com> Reviewed-by:
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Nicholas Kazlauskas authored
[Why] If we're doing backdoor load then do it entirely ourselves without invoking any of the frontdoor path to avoid potential issues with outdated tOS. [How] Check the load type and don't pass it to base if we don't want it loaded. Signed-off-by:
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Nicholas Kazlauskas authored
[Why] When we execute the first command for ASIC_INIT for command table offloading we can hit a timing scenario such that the interrupts for the inbox wptr haven't been enabled yet and the first command is ignored until the second command is sent. [How] This happens when either the SCRATCH0 is already the correct status code or autoload check is unsupported. Clear SCRATCH0 during reset. Also ensure that we don't accidentally reset the ASIC again in case of a hang by clearing GPINT while we're at it. Signed-off-by:
Chris Park <Chris.Park@amd.com> Acked-by:
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Alvin Lee authored
[Why] According to HW team, PG is dropped for NV12, but programming the registers will still cause power to be consumed, so don't program for NV12. [How] Set function pointer to NULL if NV12 Signed-off-by:
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Hersen Wu authored
Signed-off-by:
Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com> Reviewed-by:
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Hersen Wu authored
Signed-off-by:
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Alvin Lee authored
[Why] Bugs occur when TX interrupt comes in when no USB-C on board. [How] Check PHY for USB-C before enabling TX interrupt in DMCU FW. Signed-off-by:
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Dmytro Laktyushkin authored
Currently there is a minor error in scaling filter coefficients caused by truncation to fit the HW registers.This error accummulates with increased taps, but has gone unnoticed due to vast majority of scaling being done with only 4 taps. Scaling filters are now updated using HW team's filter generator which has quantization error minimization built in. Signed-off-by:
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Aric Cyr authored
[Why] Since the i2c payload allocation can fail need to check return codes [How] Clean up i2c payload allocations and check for errors Signed-off-by:
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Zhan Liu authored
[Why] core_link_read_dpcd() will invoke dm_helpers_dp_read_dpcd(), which needs to read dpcd info with the help of aconnector. If aconnector (dc->links[i]->prev) is NULL, then dpcd status cannot be read. As a result, dpcd read fails and a line of error will be printed out in dmesg.log as: "*ERROR* Failed to found connector for link!" [How] Make sure that aconnector (dc->links[i]->prev) is not NULL, then read dpcd status. Signed-off-by:
Zhan Liu <zhan.liu@amd.com> Reviewed-by:
Joseph Gravenor <Joseph.Gravenor@amd.com> Signed-off-by:
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Felix Kuehling authored
Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this race condition, perform another TLB flush after the heavy-weight one, when TC is known to be clean. Move the workaround into the low-level TLB flushing functions. This way they apply to amdgpu as well, and KIQ-based TLB flush only needs to synchronize once. Signed-off-by:
Felix Kuehling <Felix.Kuehling@amd.com> Acked-by:
Christian König <christian.koenig@amd.com> Reviewed-by:
shaoyun liu <shaoyun.liu@amd.com> Signed-off-by:
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Monk Liu authored
for bare-metal we alawys need to load sys/sos/kdb Signed-off-by:
Monk Liu <Monk.Liu@amd.com> Reviewed-by:
Evan Quan <evan.quan@amd.com> Signed-off-by:
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Shirish S authored
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by:
Shirish S <shirish.s@amd.com> Reviewed-by:
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Alex Deucher authored
Make the IP block base output debug only. Reviewed-by:
Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by:
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