- 22 Aug, 2017 15 commits
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Greg Kroah-Hartman authored
Merge tag 'phy-for-4.14_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next Kishon writes: phy: for 4.14 *) Add USB PHY driver for Ralink SoC *) Make phy-mt65xx-usb3 driver support PCIe and SATA phy *) Add mediatek directory and rename phy-mt65xx-usb3 to phy-mtk-tphy.c since it now supports USB3.0, PCIe and SATA PHYs *) Make sun4i-usb-phy driver support USB PHYs for A83T SoC *) Make phy-qcom-qmp driver support USB PHYs for IPQ8074 SoC *) Make rockchip-inno-usb2 driver support usb2-phy for rv1108 SoC *) Minor fixes in phy drivers Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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git://git.kernel.org/pub/scm/linux/kernel/git/balbi/usbGreg Kroah-Hartman authored
Felipe writes: usb: changes for v4.14 merge window Not a big pull request this time around. Only 49 non-merge commits. This pull request is, however, all over the place. Most of the changes are in the bdc driver adding support for USB Phy layer and PM. Renesas adds support for R-Car H3 ES2.0 and R-Car M3-W SoCs. Also here is PM_RUNTIME support for dwc3-keystone. UDC Core got a DMA unmap fix to make sure we only unmap requests that were, indeed, mapped. Other than these, we have a lot of cleanups, many of them adding 'const' to several places.
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Dan Carpenter authored
We want to timeout with try set to zero so this should be a pre-op instead of post-op. Signed-off-by:
Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by:
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Dan Carpenter authored
This line was indented further that it should have been. Signed-off-by:
Tony Lindgren <tony@atomide.com> Signed-off-by:
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Dan Carpenter authored
The "check" variable isn't necessarily initialized when we print it out in the debugging messages. It's a pretty haphazard affair and it doesn't matter very much what we initialize "check" to. Signed-off-by:
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Shawn Lin authored
In order to silent the 'W=1' compile warning: drivers/phy/rockchip/phy-rockchip-typec.c: In function 'tcphy_get_mode': drivers/phy/rockchip/phy-rockchip-typec.c:625:7: warning: variable 'dfp' set but not used [-Wunused-but-set-variable] Cc: Chris Zhong <zyw@rock-chips.com> Signed-off-by:
Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by:
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Frank Wang authored
This adds support usb2-phy for rv1108 SoCs and amend phy Documentation. Signed-off-by:
Frank Wang <frank.wang@rock-chips.com> Acked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Frank Wang authored
Add otg-mux property to support multiplexed interrupt in otg-port on some Rockchip SoC (e.g RV1108). Signed-off-by:
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Frank Wang authored
The otg-id/otg-bvalid/linestate interrupts are multiplexed together in otg-port on some Rockchip SoC (e.g RV1108), this patch add support for it. Signed-off-by:
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Frank Wang authored
Add rockchip,usbgrf property to support the registers of usb-phy that are distributed in grf and usbgrf on some special Rockchip SoCs (e.g RV1108). Signed-off-by:
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Frank Wang authored
The registers of usb-phy are distributed in grf and usbgrf on some Rockchip SoCs (e.g RV1108), this patch add a new rockchip,usbgrf property to support this companion grf design. Signed-off-by:
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Chen-Yu Tsai authored
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. The phy initialization procedure is very different from other SoCs, but the PMU bits are the same, with additional bits for HSIC. Signed-off-by:
Chen-Yu Tsai <wens@csie.org> Tested-by:
Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by:
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Chen-Yu Tsai authored
On the Allwinner A83T SoC, the last USB PHY is an HSIC PHY. It requires two clocks instead of one. On all Allwinner SoCs that share the common USB PHY design supported by the phy-sun4i-usb driver, the first PHY is always tied to OTG, and there is at most one HSIC PHY, typically the last. In this patch we take advantage of these known constraints and store an index in the compatible-string-related config structure describing which PHY is HSIC, needing the extra hsic_12M clock. Signed-off-by:
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Chen-Yu Tsai authored
The A83T has 3 USB PHYs, 1 for OTG, 1 for standard USB, 1 for USB HSIC. Add a compatible string for it, and describe the needed properties. Signed-off-by:
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Chen-Yu Tsai authored
The Allwinner H3 SoC has 4 USB PHYs, so it needs four sets of pmu regions, clocks, resets, and optional vbus properties. These were not described when the H3 compatible string was added. Fixes: 626a630e ("phy-sun4i-usb: Add support for the host usb-phys found on the H3 SoC") Signed-off-by:
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- 20 Aug, 2017 13 commits
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John Crispin authored
Add a driver to setup the USB phy on Mediatek/Ralink SoCs. The driver sets up power and host mode, but also needs to configure PHY registers for the MT7628 and MT7688. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
Harvey Hunt <harvey.hunt@imgtec.com> Signed-off-by:
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John Crispin authored
Add a binding for the USB phy on Mediatek/Ralink SoCs. Signed-off-by:
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Chunfeng Yun authored
reduce the boilerplate code to get the specific data Signed-off-by:
Chunfeng Yun <chunfeng.yun@mediatek.com> Signed-off-by:
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Chunfeng Yun authored
The driver is actually for T-PHY which supports USB3.0, PCIe and SATA, and supports more SoCs now, but not just only for series of mt65xx SoCs, so the name of file, data struct, functions etc with 'mt65xx' may cause misunderstanding when new SoCs are supported. Here rename them to reflect the real functions and also enhance readability. And also update MAINTAINERS file to reflect the correct driver Signed-off-by:
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Chunfeng Yun authored
add support for PCIe and SATA, also add some new compatibles. due to phy-mt65xx-usb.txt holds the bindings for all mediatek SoCs with T-PHY controller, change the name to phy-mtk-tphy.txt to reflect that. Signed-off-by:
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Ryder Lee authored
This patch adds SATA setting part. Signed-off-by:
Ryder Lee <ryder.lee@mediatek.com> Signed-off-by:
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Ryder Lee authored
This patch adds PCIe PHY setting part. Signed-off-by:
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Roger Quadros authored
The AM572x Technical Reference Manual, SPRUHZ6H, Revised November 2016 [1], shows recommended settings for the SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings. Use those settings in the driver. The TRM does not show a value for 20MHz SYS_CLK so we use something close to the 26MHz setting. [1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdfSigned-off-by:
Roger Quadros <rogerq@ti.com> [nsekhar@ti.com: add exact TRM version to commit text] Signed-off-by:
Sekhar Nori <nsekhar@ti.com> Signed-off-by:
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Vivek Gautam authored
Fixing the clk enable failure path in qcom_qmp_phy_init() and cleanup the reset control deassertion failure path in qcom_qmp_phy_com_init(). Fixes: e78f3d15 ("phy: qcom-qmp: new qmp phy driver for qcom-chipsets") Cc: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by:
Vivek Gautam <vivek.gautam@codeaurora.org> Signed-off-by:
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Varadarajan Narayanan authored
Add definitions required to enable QMP phy support for IPQ8074. Signed-off-by:
smuthayy <smuthayy@codeaurora.org> Signed-off-by:
Varadarajan Narayanan <varada@codeaurora.org> Signed-off-by:
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Varadarajan Narayanan authored
Presently, the phy pipe clock's name is assumed to be either usb3_phy_pipe_clk_src or pcie_XX_pipe_clk_src (where XX is the phy lane's number). However, this will not work if an SoC has more than one instance of the phy. Hence, instead of assuming the name of the clock, fetch it from the DT. Reviewed-by:
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Varadarajan Narayanan authored
IPQ8074 uses QMP PHY controller that provides support to PCIe and USB. Adding DT binding information for the same. Reviewed-by:
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Varadarajan Narayanan authored
The PHY outputs a clock that will act as the parent for the PHY's pipe clock. Add the name of this clock to the lane's DT node. Acked-by:
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- 18 Aug, 2017 3 commits
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Dmitry Osipenko authored
That quirk is required to make USB Ethernet gadget working on HW that can't cope with unaligned DMA. For some reason only f_ncm sets up that quirk, let's setup it directly in u_ether so other network models would have that quirk applied as well. All network models have been tested with ChipIdea UDC driver on NVIDIA Tegra20 SoC that require DMA to be aligned. Signed-off-by:
Dmitry Osipenko <digetx@gmail.com> Signed-off-by:
Felipe Balbi <felipe.balbi@linux.intel.com>
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Stephen Warren authored
When the gadget serial device has no associated TTY, do not pass any received data into the TTY layer for processing; simply drop it instead. This prevents the TTY layer from calling back into the gadget serial driver, which will then crash in e.g. gs_write_room() due to lack of gadget serial device to TTY association (i.e. a NULL pointer dereference). Signed-off-by:
Stephen Warren <swarren@nvidia.com> Signed-off-by:
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Alan Stern authored
The usb_add_gadget_udc_release() routine in the USB gadget core will sometimes but not always call the gadget's release function when an error occurs. More specifically, if the struct usb_udc allocation fails then the release function is not called, and for other errors it is. As a result, users of this routine cannot know whether they need to deallocate the memory containing the gadget structure following an error. This leads to unavoidable memory leaks or double frees. This patch fixes the problem by splitting the existing device_register() call into device_initialize() and device_add(), and doing the udc allocation in between. That way, even if the allocation fails it is still possible to call device_del(), and so the release function will be always called following an error. Signed-off-by:
Alan Stern <stern@rowland.harvard.edu> Reported-by:
Alexey Khoroshilov <khoroshilov@ispras.ru> Signed-off-by:
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- 17 Aug, 2017 1 commit
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Franklin S Cooper Jr authored
Update various properties to properly indicate their requirement depending on the SoC. Signed-off-by:
Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by:
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- 16 Aug, 2017 8 commits
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Mathias Nyman authored
bus_resume() tried to resume the same ports the bus_suspend() suspeded. This caused PLC timeouts in case a suspended device disconnected and was not in a resumable state at bus_resume(). Add a check to make sure the link state is either U3 or resuming before actually resuming the link. At the same time do some other changes such as make sure we remove wake on connect/disconnect/overcurrent also for the resuming ports, and avoid extra portsc port register writes. This improves resume time with 10ms in those PLC timeout cases where devices disconnect at suspend/resume cycle. Signed-off-by:
Mathias Nyman <mathias.nyman@linux.intel.com> Signed-off-by:
Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Mathias Nyman authored
Save 80ms device enumeration time by increasing root hub port reset time The 50ms reset signaling time is not enough for most root hub ports. Increasing the reset time to 60ms allows host controllers to finish port reset and removes a retry causing an extra 50ms delay. The USB 2 specification requires "at least 50ms" for driving root port reset. The current msleep is exactly 50ms which may not be enough if there are any delays between writing the reset bit to host controller portsc register and phy actually driving reset. On Haswell, Skylake and Kabylake xHC port reset took in average 52-59ms The 80ms improvement comes from (40ms * 2 port resets) save at enumeration for each device connected to a root hub port. more details about root port reset in USB2 section 7.1.7.5:. "Software must ensure that resets issued to the root ports drive reset long enough to overwhelm any concurrent resume attempts by downstream devices. It is required that resets from root ports have a duration of at least 50 ms (TDRSTR). Signed-off-by:
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Mathias Nyman authored
Track the port status in a human readble way each time we get a port status change event Signed-off-by:
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Mathias Nyman authored
temp and temp1 variables are used for port status (portsc) and command register. Give them more descriptive names No functional changes Signed-off-by:
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Mathias Nyman authored
Add PORTSC Port status and control register decoder to show human readable tracing of portsc register Signed-off-by:
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Mathias Nyman authored
Add definitions for all port link states defined in xhci specification for PORTSC register. Will be needed for human readable port status tracing Signed-off-by:
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Yoshihiro Shimoda authored
This patch adds support for R-Car H3 ES2.0. Since this SoC revision (or later) should use the V3 firmware, the driver needs to check the revision via soc_device_match(). Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Yoshihiro Shimoda authored
Since the firmware_name is decided by xhci-rcar.c on R-Car Gen3 now, this patch removes 2 things: - Remove struct xhci_plat_priv xhci_plat_renesas_rcar_r8a7796. - Remoce .firmware_name from xhci_plat_renesas_rcar_gen3. The behavior is the same as before. Signed-off-by:
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