- 11 Jul, 2014 2 commits
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Wolfram Sang authored
On Lager board, i2c and iic cores can be interchanged since they can be muxed to the same wires. Commit e489c2a9 ("ARM: shmobile: lager: enable i2c devices") activated the i2c cores, yet the iic cores should be default since they have the more interesting features for generic use cases, i.e. SMBUS_QUICK and DMA (yet to be supported). Reported-by:
Khiem Nguyen <khiem.nguyen.xt@renesas.com> Signed-off-by:
Wolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by:
Simon Horman <horms+renesas@verge.net.au>
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Khiem Nguyen authored
I2C bus for VDD MPU regulator is IIC3, not I2C3. Signed-off-by:
Wolfram Sang <wsa@sang-engineering.com> Signed-off-by:
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- 09 Jul, 2014 4 commits
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Simon Horman authored
As early printk is not supported when devices are initialised using DT, so remove it from the command line. Signed-off-by: -
Simon Horman authored
As early printk is not supported when devices are initialised using DT, so remove it from the command line. Signed-off-by: -
Simon Horman authored
Unify white space usage by consistently using tabs for indentation. Signed-off-by: -
Simon Horman authored
Unify white space usage by consistently using tabs for indentation. Signed-off-by:
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- 08 Jul, 2014 3 commits
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Sergei Shtylyov authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Acked-by:
Arnd Bergmann <arnd@arndb.de> [horms+renesas@verge.net.au: minor witespace changes] Signed-off-by:
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Sergei Shtylyov authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
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Sergei Shtylyov authored
Add device nodes for the R8A7791 internal PCI bridge devices. Signed-off-by:
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- 06 Jul, 2014 1 commit
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Geert Uytterhoeven authored
Add SPI device for RSPI on Genmai. On this board, only rspi4 is in use. Its bus contains a single device (a wm8978 audio codec), for which no bindings are defined yet. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by:
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- 01 Jul, 2014 1 commit
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Geert Uytterhoeven authored
Remove spaces in between tabs. Introduced by commit ff4f3eb8 ("ARM: shmobile: r8a7790: add internal PCI bridge nodes"). Signed-off-by:
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- 28 Jun, 2014 2 commits
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Kuninori Morimoto authored
Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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- 26 Jun, 2014 2 commits
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Ben Dooks authored
Enable internal AHB-PCI bridges for the USB EHCI/OHCI controllers attached to them. Signed-off-by:
Ben Dooks <ben.dooks@codethink.co.uk> Reviewed-by:
Ian Molton <ian.molton@codethink.co.uk> [Sergei: enabled PCI0] Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by:
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Ben Dooks authored
Add device nodes for the R8A7790 internal PCI bridge devices. Signed-off-by:
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- 17 Jun, 2014 25 commits
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Kuninori Morimoto authored
This patch support PIO transfer only at this point Signed-off-by:
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Phil Edworthy authored
Signed-off-by:
Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by:
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Phil Edworthy authored
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Phil Edworthy authored
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Phil Edworthy authored
This patch adds a default PCIe bus clock node. Signed-off-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> [horms+renesas@verge.net.au: resolved conflict] Signed-off-by:
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Phil Edworthy authored
This patch adds the device tree clock node for the PCIe Controller Signed-off-by:
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Phil Edworthy authored
Signed-off-by:
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Phil Edworthy authored
This patch adds a default PCIe bus clock node. Signed-off-by:
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Phil Edworthy authored
This patch adds the device tree clock node for the PCIe Controller Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by:
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Kuninori Morimoto authored
audio_clk_a/b/c are required from sound driver Signed-off-by:
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Kuninori Morimoto authored
This patch support PIO transfer only at this point Signed-off-by:
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Kuninori Morimoto authored
Signed-off-by:
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Sergei Shtylyov authored
Define the Henninger board dependent part of the I2C2 device node. Based on the Koelsch I2C2 device tree patch by Wolfram Sang. Signed-off-by:
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Simon Horman authored
A second i2c6 node was a added by 05e234a187058ee ("ARM: shmobile: koelsch dts: Add VDD MPU regulator for DVFS"). Merge this into the existing node. Also shuffle i2c nodes so they are all together. Cc: Gaku Inami <gaku.inami.xw@bp.renesas.com> Signed-off-by: -
Simon Horman authored
Due to an error when merging df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") a duplicate i2c3 node. This patch moves the duplicate and moves to old node to be closer to the other new i2c nodes. Cc: Ben Dooks <ben.dooks@codethink.co.uk> Signed-off-by: -
Magnus Damm authored
Update the Lager DTS to make use of the new unified legacy memory map where the legacy window on Lager and Koelsch have the same size. With this change in place the code gets aligned with the documentation. After update the Lager board has the following map: Bank0: 1GiB RAM (Legacy 32-bit: 0x40000000->0x7fffffff) Bank1: 3GiB RAM (LPAE area: 0x140000000->0x1ffffffff) Before the update the old map looked like this: Bank0: 2GiB RAM (Legacy 32-bit: 0x40000000->0xbfffffff) Bank1: 2GiB RAM (LPAE area: 0x180000000->0x1ffffffff) Tested with and without LPAE on r8a7790 Lager. Signed-off-by:
Magnus Damm <damm+renesas@opensource.se> Signed-off-by:
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Simon Horman authored
Due to an error when resolving conflicts df40f256b18300e1 ("ARM: shmobile: lager: add i2c1, i2c2 pins") added the i2c[12]_pins nodes to the wrong node. This patch moves them to their correct location in the pfc node. Cc: Ben Dooks <ben.dooks@codethink.co.uk> Reported-by: -
Ben Dooks authored
Add pinctrl definitions for i2c1 and i2c2 busses on the Lager board to ensure these are setup correctly at initialisation time. The i2c0 and i2c3 busses are connected to single function pins. Signed-off-by:
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Ben Dooks authored
Add i2c0, i2c1, i2c2 and i2c3 nodes to the Lager reference device tree as these busses all have devices on them that can be probed even if they are no drivers yet. Signed-off-by:
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Gaku Inami authored
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since DVS is not supported in R-CAR Gen2. - clocks phandle to the CPU clock source. This clock source is used for all the 2 CortexA15 located inside the same cluster. Signed-off-by:
Gaku Inami <gaku.inami.xw@bp.renesas.com> Acked-by:
Magnus Damm <damm@opensource.se> Signed-off-by:
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Gaku Inami authored
The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c6 node, to allow the generic CPUFreq driver to use it. Enable the i2c6 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by:
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Benoit Cousson authored
Add needed information inside CPU0 for the generic cpufreq-cpu0 driver. - voltage-tolerance = 1% It reflects the tolerance for the CPU voltage defined inside the OPP table. Due to the lack of proper OPP definition, use an arbitrary safe value. - clock-latency = 300 us Approximate worst-case latency to do a full DVFS transition for every OPPs. Due to the lack of HW information, use an arbitrary safe value. Note: The term transition-latency will be more accurate to define this value since the clock transition latency is not the only parameter that will define the overall DVFS transition. - operating-points = < kHz - uV > List of 6 operating points. All of them are using the same voltage since the valid Vmin voltage is not documented in the HW spec. - clocks phandle to the CPU clock source. This clock source is used for all the 4 CortexA15 located inside the same cluster. Signed-off-by:
Benoit Cousson <bcousson+renesas@baylibre.com> [gaku.inami.xw@bp.renesas.com: Change the setting of OPPs for ES2.0] Signed-off-by:
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Benoit Cousson authored
The CA15 cluster is capable of voltage scaling. Add the regulator in the i2c3 node, to allow the generic CPUFreq driver to use it. Enable the i2c3 pin mux and the device node as well since the da9210 is connected to that bus. Note: In R-CAR Gen2, each frequency is using the same voltage, and DVS control is not used. Therefore, this patch set the voltage(Vmin/Vmax) to 1000mv. Signed-off-by:
Benoit Cousson <bcousson@baylibre.com> [gaku.inami.xw@bp.renesas.com: Changes Vmin for disabling DVS] Signed-off-by:
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Geert Uytterhoeven authored
Add clocks for the SYS-DMAC0 and SYS-DMAC1 hardware blocks. Cfr. the r8a7790 version by Ben Dooks. Signed-off-by:
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