- 19 May, 2020 1 commit
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Sandeep Maheswaram authored
Convert QMP PHY bindings to DT schema format using json-schema. Signed-off-by:
Sandeep Maheswaram <sanm@codeaurora.org> Link: https://lore.kernel.org/r/1589510358-3865-2-git-send-email-sanm@codeaurora.orgSigned-off-by:
Vinod Koul <vkoul@kernel.org>
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- 18 May, 2020 13 commits
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Sanket Parmar authored
Updated values of USB3 related Sierra PHY registers. This change fixes USB3 device disconnect issue observed while enternig U1/U2 state. Signed-off-by:
Sanket Parmar <sparmar@cadence.com> Link: https://lore.kernel.org/r/1589804053-14302-1-git-send-email-sparmar@cadence.comReviewed-by:
Roger Quadros <rogerq@ti.com> Signed-off-by:
Kishon Vijay Abraham I <kishon@ti.com>
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Roger Quadros authored
The SERDES PHY can support USB super-speed lane. Add support for that. Signed-off-by:
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Roger Quadros authored
The max_register property must be set in order to show up the registers in debugfs. Signed-off-by:
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Bharat Gooty authored
During different reboot cycles, USB PHY PLL may not always lock during initialization and therefore can cause USB to be not usable. Hence do not use internal FSM programming sequence for the USB PHY initialization. Fixes: 4dcddbb3 ("phy: sr-usb: Add Stingray USB PHY driver") Signed-off-by:
Bharat Gooty <bharat.gooty@broadcom.com> Signed-off-by:
Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Link: https://lore.kernel.org/r/20200513173947.10919-1-rayagonda.kokatanur@broadcom.comSigned-off-by:
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Yoshihiro Shimoda authored
This patch adds support for r8a77961 (R-Car M3-W+). Signed-off-by:
Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Reviewed-by:
Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/1585301636-24399-5-git-send-email-yoshihiro.shimoda.uh@renesas.comAcked-by:
Rob Herring <robh@kernel.org> Signed-off-by:
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Yoshihiro Shimoda authored
Convert Renesas R-Car generation 3 USB 3.0 PHY bindings documentation to json-schema. Signed-off-by:
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Yoshihiro Shimoda authored
This patch adds support for r8a77961 (R-Car M3-W+). Signed-off-by:
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Yoshihiro Shimoda authored
Convert Renesas R-Car generation 3 USB 2.0 PHY bindings documentation to json-schema. Signed-off-by:
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Bjorn Andersson authored
It's possible that struct qmp_phy_cfg->regs references an array that is smaller than the possible register lookups that is going to be performed, with the resulting out-of-bounds read resulting in undefined behavior. One such example is when during qcom_qmp_phy_com_init() performs a qphy_setbits() on entry QPHY_PCS_POWER_DOWN_CONTROL (i.e. 17) with msm8996_ufsphy_regs_layout only being 12 entries long. Solve this by inflating all "regs_layout" arrays to ensure that any remaining entries are zero-initialized, as expected by the code. Fixes: e4d8b05a ("phy: qcom-qmp: Use proper PWRDOWN offset for sm8150 USB") Signed-off-by:
Bjorn Andersson <bjorn.andersson@linaro.org> Link: https://lore.kernel.org/r/20200515013643.2081941-1-bjorn.andersson@linaro.orgSigned-off-by:
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Roger Quadros authored
Move private definitions from header to phy-omap-usb2.c file. Get rid of unused data structures usb_dpll_params and omap_usb_phy_type. Signed-off-by:
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Rikard Falkeborn authored
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 7831 3144 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o After: text data bss dec hex filename 7959 3016 128 11103 2b5f drivers/phy/broadcom/phy-bcm-ns2-usbdrd.o Signed-off-by:
Rikard Falkeborn <rikard.falkeborn@gmail.com> Link: https://lore.kernel.org/r/20200516120441.7627-2-rikard.falkeborn@gmail.comSigned-off-by:
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Rikard Falkeborn authored
A number of structs were not modified and can therefore be made const to allow the compiler to put them in read-only memory. In order to do so, update a few functions that don't modify there input to take pointers to const. Before: text data bss dec hex filename 15511 6448 64 22023 5607 drivers/phy/broadcom/phy-brcm-usb.o After: text data bss dec hex filename 16058 5936 64 22058 562a drivers/phy/broadcom/phy-brcm-usb.o Signed-off-by:
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Rikard Falkeborn authored
phy_ops are never modified and can therefore be made const to allow the compiler to put it in read-only memory. Before: text data bss dec hex filename 4310 1244 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o After: text data bss dec hex filename 4438 1116 0 5554 15b2 drivers/phy/broadcom/phy-bcm-sr-usb.o Signed-off-by:
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- 15 May, 2020 7 commits
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Peter Chen authored
The .init is used for one-time PHY's initialization, and .power_on is called many times during the device lifecycle. Signed-off-by:
Peter Chen <peter.chen@nxp.com> Link: https://lore.kernel.org/r/20200513125605.5545-1-peter.chen@nxp.comSigned-off-by:
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Martin Blumenstingl authored
The 3.10 vendor kernel sets the ACA_ENABLE bit on Meson8b, Meson8m2 and GXBB, but not on Meson8. Add a compatible string for Meson8m2 which also sets that bit. While here, also update the Kconfig text and MODULE_DESCRIPTION. Signed-off-by:
Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by:
Thomas Graichen <thomas.graichen@gmail.com> Link: https://lore.kernel.org/r/20200512222424.549351-7-martin.blumenstingl@googlemail.comSigned-off-by:
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Martin Blumenstingl authored
The vendor driver unsets the set_iddig bit during power-on as well and sets it when suspending the PHY. I did not notice this in the vendor driver first, because it's part of the dwc_otg driver there (instead of their PHY code). While here, also add all other REG_DBG_UART register bit definitions. Signed-off-by:
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Martin Blumenstingl authored
Skip setting REG_ADP_BC_ACA_ENABLE on Meson8 SoCs and polling for the REG_ADP_BC_ACA_PIN_FLOAT bit. The vendor also skips this part on Meson8 SoCs. This fixes initialization of the host-only USB PHY on Meson8 which would otherwise fail with "USB ID detect failed!". Fixes: 4a3449d1 ("phy: meson8b-usb2: add support for the USB PHY on Meson8 SoCs") Reported-by:
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Martin Blumenstingl authored
Using a MMIO regmap and switch to regmap_update_bits() to simplify the code in the driver. Also switch to devm_platform_ioremap_resource() instead of open-coding it. No functional changes intended. Signed-off-by:
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Martin Blumenstingl authored
The USB2 PHY on Meson8m2 is identical to the one on Meson8b but different to the one on Meson8. The only known difference is that Meson8 does not set the ACA_ENABLE bit while Meson8b and Meson8m2 do. Add an explicit compatible string for Meson8m2 so those differences can be taken care of. Signed-off-by:
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Martin Blumenstingl authored
Now that we have the DT validation in place, let's convert the device tree bindings for the Amlogic Meson8, Meson8b, Meson8m2 and GXBB USB2 PHY over to a YAML schema. While here, also add the fallback compatible string "amlogic,meson-gxbb-usb2-phy" which is already used in arch/arm/boot/dts/meson{,8,8b}.dtsi. Signed-off-by:
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- 13 May, 2020 4 commits
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Geert Uytterhoeven authored
The Intel eMMC PHY is only present on Intel Lightning Mountain SoCs. Add an architecture dependency to the PHY_INTEL_EMMC config symbol, to avoid asking the user about it when configuring a kernel for a non-x86 architecture. Signed-off-by:
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Wei Yongjun authored
Fix to return negative error code from some error handling cases instead of 0, as done elsewhere in this function. Fixes: 091876cc ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Reported-by:
Hulk Robot <hulkci@huawei.com> Signed-off-by:
Wei Yongjun <weiyongjun1@huawei.com> Acked-by:
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Christophe JAILLET authored
Axe a clk that is unused in the driver. Signed-off-by:
Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by:
Tony Lindgren <tony@atomide.com> Link: https://lore.kernel.org/r/20200507203127.202197-1-christophe.jaillet@wanadoo.frSigned-off-by:
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Jonathan Bakker authored
The USB phy takes some time to reset, so make sure we give it to it. The delay length was taken from the 4x12 phy driver. This manifested in issues with the DWC2 driver since commit fe369e18 ("usb: dwc2: Make dwc2_readl/writel functions endianness-agnostic.") where the endianness check would read the DWC ID as 0 due to the phy still resetting, resulting in the wrong endian mode being chosen. Signed-off-by:
Jonathan Bakker <xc-racer2@live.ca> Link: https://lore.kernel.org/r/BN6PR04MB06605D52502816E500683553A3D10@BN6PR04MB0660.namprd04.prod.outlook.comSigned-off-by:
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- 07 May, 2020 2 commits
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Peter Chen authored
Cadence SALVO PHY is a 28nm product, and is only used for USB3 & USB2. According to the Cadence, this PHY is a legacy Module, and Sierra and Torrent are later evolutions from it, and their sequence overlap is minimal, meaning we cannot reuse either (Sierra & Torrent) of the PHY drivers. Signed-off-by:
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Peter Chen authored
Add Cadence SALVO PHY binding doc, this PHY is a legacy module, and is only used for USB3 and USB2. Signed-off-by:
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- 06 May, 2020 1 commit
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Wesley Cheng authored
Fix errors reported by dt_binding_check, due to missing required regulators in the example node. Fixes: f06b9fc9 ("dt-bindings: phy: Add binding for qcom,usb-snps-femto-v2") Signed-off-by:
Wesley Cheng <wcheng@codeaurora.org> Reported-by:
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- 05 May, 2020 5 commits
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Wesley Cheng authored
The UFS QMP v4 PHY has a largely different register set versus USB and PCIe. Rename the register offsets to denote that the value is specific for the UFS PCS register. Signed-off-by:
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Wesley Cheng authored
The register map for SM8150 QMP USB SSPHY has moved QPHY_POWER_DOWN_CONTROL to a different offset. Allow for an offset in the register table to override default value if it is a DP capable PHY. Signed-off-by:
Manu Gautam <mgautam@codeaurora.org> Link: https://lore.kernel.org/r/1588636467-23409-5-git-send-email-wcheng@codeaurora.orgSigned-off-by:
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Jack Pham authored
Add support for SM8150 QMP USB3 PHY with the necessary initialization sequences as well as additional QMP V4 register definitions. Signed-off-by:
Jack Pham <jackp@codeaurora.org> Signed-off-by:
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Wesley Cheng authored
This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by:
Philipp Zabel <pza@pengutronix.de> Reviewed-by:
Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.orgSigned-off-by:
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Wesley Cheng authored
This binding shows the descriptions and properties for the Synopsis Femto USB PHY V2 used on QCOM platforms. Signed-off-by:
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- 04 May, 2020 2 commits
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Robert Marko authored
This patch adds the binding documentation for the HS/SS USB PHY found inside Qualcom Dakota SoCs. Signed-off-by:
John Crispin <john@phrozen.org> Signed-off-by:
Robert Marko <robert.marko@sartura.hr> Reviewed-by:
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Robert Marko authored
Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by:
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- 28 Apr, 2020 1 commit
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Bjorn Andersson authored
The SM8250 UFS PHY can run off the same initialization sequence as SM8150, but add the compatible to allow future changes. Signed-off-by:
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- 24 Apr, 2020 1 commit
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Jyri Sarha authored
For DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to "cdns,phy-type"-properties found in link subnodes under the managed serdes (see "ti,sierra-phy-t0" and "ti,j721e-serdes-10g" devicetree bindings for details). All other values of "cdns,phy-type"-property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable. Signed-off-by:
Jyri Sarha <jsarha@ti.com> Signed-off-by:
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- 12 Apr, 2020 3 commits
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Linus Torvalds authored
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Linus Torvalds authored
This sorts the actual field names too, potentially causing even more chaos and confusion at merge time if you have edited the MAINTAINERS file. But the end result is a more consistent layout, and hopefully it's a one-time pain minimized by doing this just before the -rc1 release. This was entirely scripted: ./scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS --order Requested-by:
Joe Perches <joe@perches.com> Signed-off-by:
Linus Torvalds <torvalds@linux-foundation.org>
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Linus Torvalds authored
They are all supposed to be sorted, but people who add new entries don't always know the alphabet. Plus sometimes the entry names get edited, and people don't then re-order the entry. Let's see how painful this will be for merging purposes (the MAINTAINERS file is often edited in various different trees), but Joe claims there's relatively few patches in -next that touch this, and doing it just before -rc1 is likely the best time. Fingers crossed. This was scripted with /scripts/parse-maintainers.pl --input=MAINTAINERS --output=MAINTAINERS but then I also ended up manually upper-casing a few entry names that stood out when looking at the end result. Requested-by:
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