- 27 Jan, 2017 40 commits
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Nicolai Hähnle authored
Skip amdgpu_gem_va_update_vm when shadow the page directory is swapped out. Clean up the check for non-shadow BOs as well using the new helper function. This fixes a crash with the stack trace: amdgpu_gem_va_update_vm -> amdgpu_vm_update_page_directory -> amdgpu_ttm_bind -> amdgpu_gtt_mgr_alloc Signed-off-by:
Nicolai Hähnle <nicolai.haehnle@amd.com> Reviewed-by:
Chunming Zhou <david1.zhou@amd.com> Reviewed-by:
Christian König <christian.koenig@amd.com> Signed-off-by:
Alex Deucher <alexander.deucher@amd.com>
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Nicolai Hähnle authored
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Nicolai Hähnle authored
This catches evictions of shadow page tables from the GART. Since shadow page tables are always stored in system memory, amdgpu_bo_move is never called for them. This fixes a crash during command submission that occurs when only a shadow page table and no other BOs were evicted since the last submission. Fixes: 1baa439f ("drm/amdgpu: allocate shadow for pd/pt bo V2") Signed-off-by:
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Nicolai Hähnle authored
Ensure that the driver can listen to evictions even when they don't take the path through ttm_bo_driver::move. This is crucial for amdgpu, which relies on an eviction counter to skip re-binding page tables when possible. Signed-off-by:
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Rex Zhu authored
1. disable vce cg when vce hw initialize. 2. initizlize vce clock to 10KHz fo dgpu, so no need to set bypass clock to vce. Change-Id: I934c2c4820cc95c1bfa2fa41ff0f40a0d3cd1c40 Signed-off-by:
Rex Zhu <Rex.Zhu@amd.com> Reviewed-by:
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Rex Zhu authored
in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as profile_normal, set lowest sclk profile_min_mclk: fix sclk as profile_normal, set lowest mclk profile_peak: set highest sclk and mclk, power and thermal not sustainable profile_exit: exit profile mode. enable gfx cg/lbpw feature. Signed-off-by:
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Rex Zhu authored
Updating SQ DIDT settings and block mask so SQ uses PCC on Polaris11. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
following firmware's request. Signed-off-by:
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Rex Zhu authored
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Huang Rui authored
Signed-off-by:
Huang Rui <ray.huang@amd.com> Reviewed-by:
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
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Huang Rui authored
Suggested-by:
Felix Kuehling <Felix.Kuehling@amd.com> Signed-off-by:
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Huang Rui authored
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Xiangliang Yu authored
Call detection function driectly, so remove the interface. V2: ci and si also need to call the detect function. Reviewed-by:
Monk Liu <monk.liu@amd.com> Acked-by:
Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by:
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Xiangliang Yu authored
Move the detection forward into vi_set_ip_blocks function, then add ip blocks virtualization need if device is VF. V2: add ip blocks according to asic type. Reviewed-by:
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Xiangliang Yu authored
Use acronym to rename fields to make easy to spell out. Signed-off-by:
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Xiangliang Yu authored
KIQ is queue-memory based initialization method: setup KIQ queue firstly, then send command to KIQ to setup other queues, without accessing registers. For virtualization, need KIQ to access virtual function registers when running on guest mode. V2: use amdgpu_bo_create/free_kernel to allocate BO. Signed-off-by:
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Amber Lin authored
PCI I/O bar can be disabled in VBIOS to save the resource. It is often disabled in large aperture VBIOS. Don't call it an error. Signed-off-by:
Amber Lin <Amber.Lin@amd.com> Acked-by:
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Rex Zhu authored
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Rex Zhu authored
1. delete asic_smum_init functions, export asic private functions to smumgr directly, make code more readable. 2. create asic private data in asic_init_func. Signed-off-by:
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Rex Zhu authored
add pp_smu7_thermal_fini function to free related data when smu7_hwmgr_fini. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
struct smumgr/hwmgr will be freed on amd_powerplay_destory and if we free them in one of asic private functions, other private date may not be freed. for example: power state and power table in hwmgr. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
v2: add pp_check function to check pp_instance valid. 1. powerplay export two new interface to amdgpu, amd_powerplay_create/amd_powerplay_destroy. 2. create pp_instance/smumgr/hwmgr/eventmgr in early init, destroy them when lata_fini. 3. in sw_init, create and init asic private smumgr data, and free them when sw_fini. 4. in hw_init, create and init asic private hwmgr data, and free them when hw_fini. 5. export powerplay state: PP_DPM_DISABLED. when user disabled powerplay or hwmgr/eventmgr init failed, powerplay return this state to amdgpu. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
In some case, App need to run under max stable clock. so export profiling mode: GFX CG was disabled. and user can select the max stable clock of the device. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
need to release failed smu firmware before load another firmware. Signed-off-by:
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Rex Zhu authored
cz_smu_init will be called in sw_init. so it should not touch other blocks's firmware as they were not ready. Signed-off-by:
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Rex Zhu authored
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Rex Zhu authored
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Rex Zhu authored
The powerplay implementation has been the default for a while now. Signed-off-by:
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Huang Rui authored
Signed-off-by:
Edward O'Callaghan <funfunctor@folklore1984.net> Signed-off-by:
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