- 10 Dec, 2015 10 commits
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Wei Chen authored
Remove write-protect and chip-selector pins from nand pin group. And then create two separate pin groups for these two pin. So the nand driver can choose correct pin groups as board desgin: For example: 1. nand without wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx>; }; 2. nand with wp nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx>; }; 3. nand with cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_cs_pmx>; }; 4. nand with wp&cs: nand@17050000 { pinctrl-0 = <&nd_df_basic_pmx &nd_df_wp_pmx &nd_df_cs_pmx>; }; Signed-off-by:Wei Chen <Wei.Chen@csr.com> Signed-off-by:
Barry Song <Baohua.Song@csr.com> Signed-off-by:
Linus Walleij <linus.walleij@linaro.org>
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Yonghui Zhang authored
The sd9 pin mux with sd3 and it is selected by SYS2PCI_SDIO9SEL. This makes the codes ugly since the register is not in pinctrl module. Signed-off-by:
Yonghui Zhang <yonghui.zhang@csr.com> Signed-off-by:
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Wei Chen authored
The nand in atlas7 has two chip select line. But in most time, the nand only has one chip, so only one chip select line is enough. The nand driver select this new pin group can free one chip select line for other modules to avoid pin conflict. Signed-off-by:
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Robert Jarzmik authored
As the pxa architecture, at least for pxa27x, supports pin control, activate it in the pinctrl tree. Signed-off-by:
Robert Jarzmik <robert.jarzmik@free.fr> Signed-off-by:
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Robert Jarzmik authored
Add the pxa27x architecture, which is a pxa2xx with 128 pins. The registers spacing, and pins logic is common to pxa2xx, only the pins and their alternate function are specific to pxa27x. Signed-off-by:
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Robert Jarzmik authored
Add pin configuration for pxa2xx architectures. PXA doesn't provide any bias, push, pull capabilities. The only capability is to set a state for the pins when the platform enter sleep or deep sleep mode. The state of a pin is set by : - whether the GPIO direction was input or output - if it is output, a register set programs whether the pin should be held to ground or VccIO Signed-off-by:
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Robert Jarzmik authored
The driver is inspired from the sunxi driver. The pxa architecture specificities leading to the driver are : - each pin has 8 possible alternate functions - 4 of these are output kind - 4 of these are input kind - there is always a "gpio input" and "gpio output" function - the function matrix is very scattered : - some functions can be found on 5 different pads - the number of functions is greater than the number of pins - there is no "topology" grouping of pins (such as all SPI in one corner of the die) Signed-off-by: -
Robert Jarzmik authored
Add a pincontrol driver for pxa2xx architecture, encompassing all pxa25x and pxa27x variants. This is only the pin muxing part of the driver. One specific consideration is also the memory space (MMIO), which is intertwined with the GPIO registers. To make things worse, the GPIO direction register also affect pin muxing, as it chooses the "kind" of pin, ie. the 4 output functions or 4 input functions. The mapping between pinctrl notions and PXA Technical Reference Manual is as follows : - a pin is obviously a pin - a group is also a pin, ie. group P101 is the pin 101 - a mux function is an alternate function (ie. gpio-in, gpio-out, MMCLK, BTRTS, etc ...) The individual architecture (pxa27x, pxa25x) instantiate a pin control by providing a table of pins, each pin being provided a list of PXA_FUNCTION (alternate functions). Signed-off-by:
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Robert Jarzmik authored
Add the pinctrl pxa drivers to the pxa maintained files. Signed-off-by:
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Linus Walleij authored
Merge branch 'sh-pfc-for-v4.5' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel
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- 09 Dec, 2015 1 commit
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Sebastian Hesselbarth authored
Common MVEBU pinctrl driver core gets an array of controls to modify a specific set of registers and an array of modes for each pingroup from each of the different SoC families of MVEBU. Some SoC families comprise different variants that differ in available pingroups and also controls, but to ease driver development, we can pass a variant mask to disable specific pingroups for some variants. However, controls are limited to the true number of pinctrl groups avaiable on a variant. Now, when pinctrl core driver parses over above arrays, it tries to match modes with available controls and complains about missing controls for modes that are passed to the core but actually are not avaiable on a variant with: kirkwood-pinctrl f1010000.pin-controller: unknown pinctrl group 36 This warning is a false-positive and annoying, so move the warning after we checked the variant mask for each mode setting. Also, if there is no supported setting for this variant, do not complain at all. Signed-off-by:
Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Reported-by:
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- 08 Dec, 2015 12 commits
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Geert Uytterhoeven authored
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by:
Geert Uytterhoeven <geert+renesas@glider.be> Acked-by:
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Geert Uytterhoeven authored
Add pins, groups, and a function for SCIF_CLK, which is the external clock source for the Baud Rate Generator for External Clock (BRG) on (H)SCIF. Signed-off-by:
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Geert Uytterhoeven authored
Add pins, groups, and a function for the 4 MSIOF devices. Note that the pin function name of MSIOF3 is named BBIF1. Signed-off-by: -
Geert Uytterhoeven authored
The 12 data pins of LCD2 are numbered 0..11, not 0..12. Signed-off-by: -
Geert Uytterhoeven authored
The 12 data pins of LCD1 are numbered 0..11, not 0..12. Signed-off-by: -
Geert Uytterhoeven authored
The 8 data pins of the Compact Flash Interface are numbered 0..7, not 0..8. Signed-off-by: -
Geert Uytterhoeven authored
Extracted from a big patch by Takeshi Kihara. Signed-off-by:
Takeshi Kihara <takeshi.kihara.df@renesas.com> [geert: Correct MSIOF3 TXD_A/RXD_A pins] Signed-off-by:
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Geert Uytterhoeven authored
Pins that (1) can be configured as either GPIO or a single peripheral function, and (2) that don't need configuration in an IPSRx register, should still be listed in the pinmux_data[] array. Else selecting the peripheral function fails with e.g.: sh-pfc e6060000.pfc: cannot locate data/mark enum_id for mark 1281 (mark 1281 is MSIOF0_SCK_MARK). Signed-off-by: -
Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
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- 01 Dec, 2015 12 commits
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Qipeng Zha authored
The group size for registers PADCFGLOCK, HOSTSW_OWN, GPI_IS, GPI_IE, are not 24 for Broxton, Add a parameter to allow different platform to set correct value. Signed-off-by:
Qi Zheng <qi.zheng@intel.com> Signed-off-by:
Qipeng Zha <qipeng.zha@intel.com> Acked-by:
Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by:
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Yingjoe Chen authored
The returned configs from pinconf_generic_parse_dt_config() is duplicated from original. Make it clear it must be freed when no longer necessary. Signed-off-by:
Yingjoe Chen <yingjoe.chen@mediatek.com> Signed-off-by:
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Masahiro Yamada authored
Signed-off-by:
Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by:
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Masahiro Yamada authored
CONFIG_PINCTRL_SPEAR is more suitable than CONFIG_PLAT_SPEAR to guard the drivers/pinctrl/spear/ directory. Signed-off-by:
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Masahiro Yamada authored
CONFIG_PINCTRL_MVEBU is more suitable than CONFIG_PLAT_ORION to guard the drivers/pinctrl/mvebu/ directory. Signed-off-by:
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Masahiro Yamada authored
CONFIG_PINCTRL_BERLIN is more suitable than CONFIG_ARCH_BERLIN to guard the drivers/pinctrl/berlin/ directory. Signed-off-by:
Jisheng Zhang <jszhang@marvell.com> Acked-by:
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Masahiro Yamada authored
There is a plan to support more pinctrl drivers for this SoC family. Move the driver entries into a sub menu by using "menuconfig". Also, add the missing dependency "depends on OF && MFD_SYSCON". Signed-off-by:
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Stephen Boyd authored
Update the driver and binding for pm8994-mpp devices. Cc: <devicetree@vger.kernel.org> Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com> Signed-off-by:
Stephen Boyd <sboyd@codeaurora.org> Acked-by:
Rob Herring <robh@kernel.org> Acked-by:
Björn Andersson <bjorn.andersson@sonymobile.com> Signed-off-by:
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Stephen Boyd authored
Update the binding and driver for pm8994-gpio devices. Cc: <devicetree@vger.kernel.org> Cc: "Ivan T. Ivanov" <iivanov@mm-sol.com> Signed-off-by:
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Joonwoo Park authored
Add initial pinctrl driver to support pin configuration with pinctrl framework for msm8996. Cc: <devicetree@vger.kernel.org> Signed-off-by:
Joonwoo Park <joonwoop@codeaurora.org> [sboyd@codeaurora.org: Remove duplicate entries and enums] Signed-off-by:
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Stephen Boyd authored
The number of interrupts is always equal to the number of pins provided by the PMIC gpio and MPP hardware blocks. Count the number of irqs to figure out the number of pins instead of adding more compatible strings or doing math on the reg property. This should make the code more generic and ease the number of changes we have to make to the driver for each new pmic revision. Cc: Ivan T. Ivanov <iivanov@mm-sol.com> Signed-off-by:
Andy Gross <agross@codeaurora.org> Reviewed-by:
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Timur Tabi authored
The driver doesn't report an error message if the ACPI tables are missing the num-gpios property (which indicates how many GPIOs there are on this SOC), and it didn't check to ensure that the mallocs didn't fail. Signed-off-by:
Timur Tabi <timur@codeaurora.org> Reviewed-by:
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- 30 Nov, 2015 5 commits
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Kuninori Morimoto authored
Many SoC needs each PORT_GP_x() macros, but we can share/reuse same one. Signed-off-by:
Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by:
Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by:
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Geert Uytterhoeven authored
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Geert Uytterhoeven authored
Cfr. Manual Errata for Rev 0.50 of the R-Car Gen3 datasheet. This has no user-visible impact. Signed-off-by:
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Geert Uytterhoeven authored
On r8a7795, PORT_GP_x() is a macro for defining GPIOs 0..x. In all other sh-pfc code, PORT_GP_x() is a macro for defining GPIOs 0..(x-1). Make the r8a7795 macro definitions consistent with the rest of the sh-pfc codebase. Signed-off-by:
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Geert Uytterhoeven authored
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